HES-DVM Hybrid Verification Platform

HES-DVM™ is a fully automated and scalable hybrid verification environment for SoC and ASIC designs. Utilizing the latest co-emulation standards like SCE-MI or TLM and newest FPGA technology, hardware and software design teams obtain early access to the hardware prototype of the design. Working concurrently with one another they develop and verify high-level code with RTL accuracy and speed-effective SoC emulation or prototyping models reducing test time and a risk of silicon re-spins.

HES-DVM™ provides verification teams with multiple use modes including both emulation and physical prototyping techniques enabling SoC teams to work on a single platform.

 

 

Emulation Modes

Emulation modes include simulation acceleration, transaction level co-emulation and in-circuit emulation for chip and system level verification of SoC and ASIC designs. These use models enable many applications such as hardware and software co-verification utilizing TLM wrappers and high-speed AXI or AHB bus transactors to connect design residing in hardware with Virtual Platforms. Also included are powerful debugging tools that allow for 100% visibility into modules running in the FPGA, making the HES-DVM emulation platform as easy to use as an RTL simulator.

 

Key Features

Supported FPGA Boards

 

Verification Interfaces

 

Automated Design Setup

 

Debugging Capabilities

 

Physical Prototyping

Physical prototyping enables the highest clock rates, often close to the target ones, so it is ideal for verification in the real environment with devices sending and receiving real data streams. The HES-DVM aids in design partitioning, clock conversion and mapping to FPGA and facilitates designing inter-chip connections that utilize serialization techniques to overcome limitation of FPGA I/O.

 

Key Features

Supported FPGA Boards

 

Automated Design Setup

 

Scalability and Reuse

Enabling scalability is the core objective of the HES-DVM™ development team, and this is what makes our solution unique. The FPGA technology is evolving so fast that it is wise to be always on the cutting edge. Instead of being limited to a fixed dedicated hardware emulation platform, Aldec continues to develop an open architecture that can be quickly migrated to the next generation FPGA technology, and also used with custom in-house made prototyping boards.



Printed version of site: www.aldec.com/en/products/emulation/hes-dvm