Read what users have to say about Active-HDL vs. Mentor ModelSIM in John Cooley’s independent report published at: Aldec crushes Mentor Article
"Thanks for the incredible seminar on assertions. I would like to thank you for arranging such a wonderful seminar with no marketing stuff in that. Overall I rate it 'Best' or 'Exceeded my Expectations' range."
Intel - Engineering Manager
"[Riviera's] MatLab co-sim helped me catch an error in the Xilinx DSP48e mathematical operations. The error would have propagated the design and not been seen until in lab testing. In the past, this kind of error would have cost 2-4 weeks to isolate and correct. In addition, the direct MatLab link allows for a 30 second advanced simulation with full sim/stim (simulation and stimulation) capability of our top-level design that would have taken 5-6 hours in the past due to using text files for data transfers."
Lockheed Martin - Hardware Design Engineer
"The simulation performance and user interface of Aldec's Active-HDL are simply superb. Every feature I needed was thoughtfully and elegantly in place. Thanks to Aldec's support team, learning how to simulate a new and rather complex design took nearly no time at all. It is quite clear that Aldec's engineers have left no stone unturned in their quest for excellence."
Jacob Yalcin - Senior Systems Engineer Equinox Corporation
"Infra-Com's highly sophisticated wireless communication digital ASICs project had a very tight schedule - One of the main benefits of engaging with Aldec for the design entry and simulation of our ASIC chipset was to reduce the time to market and risks. For Infra-Com, two generations of successful products make Aldec a proven solution for the ASIC chipsets."
Uri Kanonich - Infra-Com's COO
"Aldec's simulator is a tremendous value for money. For the price, nothing near that good is available on the market. Aldec's Active-HDL environment satisfies all our requirements for source code creation and debugging. It has a source code debugger, a waveform viewer, data flow diagrams generated on the fly. A memory viewer is also available, an important touch for a company like ours that develops processor cores. While we use simulators from other parties for the sake of script compliance testing, we have relied on Aldec's simulator as the key tool in our development process for several years."
Wojciech Sakowski CSO, Evatronix A silicon Intellectual Property (IP) provider
"I want to thank you for conducting Active-HDL training at Transcore. That is the kind of "after-the-sale" support most companies would be envious of!! Aldec remains a cut above the rest."
Lawrence Gorton Transcore Amtech Technology Center
“I’ve been in the field for nearly 10 years and have worked in department of defense, aerospace, and telecommunications industries. I have found that Aldec’s powerful Active-HDL accommodates both experienced designers as well as new college graduates. Its unique interface is friendly and easy to use. Because it supports multiple FPGA devices, I consider Aldec a staple in VHDL design and simulation.”
Preston Adams – Hardware Design and Analysis Engineer
"Active-HDL is very user friendly and anyone can use the tool without much difficulty. Simulator performance is very fast and waveform portability using cut/paste is a very useful feature for documentation purposes. The block diagram entry is again a great feature for implementing top down design approach. Our groups overall productivity has increased substantially because of Active-HDL."
Venkatesan Sivaprakasam, Deputy Engineer, SED, Electronics Corporation of India Limited, Hyderabad, India
"I was able to attend and thanks for the follow up. I'd like to also add to the positive feedback - it was very technical and very informative - perfect for us engineers. Kudos to you.
Comit Systems, Inc
"Comtech EF Data engineering has used and compared many other FPGA design entry and simulation tools. Active-HDL far surpass the competition in tool features and user-friendly interfaces; with a much lower price-tag."
Dennis Bennett, Comtech EF Data