Denver, CO, USA – November 18, 2019, Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for SoC and FPGA designs, is exhibiting at Supercomputing19 to be held on November 18-21, 2019 in Denver, Colorado, and will be demonstrating a powerful multi-FPGA partitioning software for multi-FPGA-based algorithm accelerators.
“We will showcase the recently introduced automatic FPGA partitioning feature of our popular HES-DVM™ tool, our fully automated and scalable hybrid verification environment for large SoC designs,” said Louie De Luna, Director of Marketing. “Manual partitioning of designs with multiple FPGAs, can take days or even weeks, whereas HES-DVM can perform the task in minutes.”
The partitioning software can be used with Aldec’s HES Prototyping boards and as well as 3rd party prototyping boards.
See the Aldec demos at SC19, Booth#228
About Aldec
Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, High-Performance Computing Platforms, Embedded Development Systems, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com