by Benard Murphy
I earlier wrote a piece to make you aware of a webinar to be hosted by Aldec on some of their capabilities for partitioning large designs for prototyping. That webinar has now been broadcast and I have provided a link to the recorded version at the end of this piece. The webinar gets into the details of how exactly you would use the software to optimally partition; here I'll revisit why this is important, adding a realization for me on the pros and cons of automatic versus guided partitioning.
Prototyping a hardware design on a FPGA platform is especially important for software development, debug and regression while the ultimate ASIC hardware is still in development or even in the early stage when your bidding on an RFP or hoping to persuade VCs/angels that you have an investment-worthy idea. They’re also the best way to test in-system behavior with external interfaces like video streams, storage interfaces and a wealth of communications options.
For the rest of this article, please visit SemiWiki.