By Sergei Zaychenko
Automated design rule checking, or linting, has been around in RTL verification for at least a couple decades, yet still many HDL designers completely ignore this simple yet very powerful bug hunting method. Why would a busy designer need to run this annoying warning generator? The hostility against using conventional linting tools is often explained by the enormous amount of output noise, limited configurability, ambiguous reporting, and inability to capture a high-level designer’s intent. FPGA users also complain about the lack of vendor libraries support. Whether it’s an ASIC or FPGA, the presence of IP blocks creates an extra challenge for DRC tools, as IPs are often tool-generated or encrypted.
While there are a couple of well-known, mature DRC-based verification tools on the EDA market targeting the large-scale ASIC segment, they also come with an annual license cost that exceeds the price of a new four-wheel SUV. The use of auto-formal methods applied to aspects such as CDC protocol checks and MCP validation, as well as the handling of UPF-based power models and taking physical cell properties into account, indeed make those linting tools very powerful. But is this capacity really necessary for a hypothetical mid-range FPGA project relying on the native vendor’s backend implementation tools...
For the rest of this article, visit SemiConductorEngineering.