By Don Dingee
Many tools find clock domain crossings (CDCs) in FPGA designs. Some don’t find the right ones since they don’t comprehend things like in-house synchronizer constructs. Some find too many based on misunderstanding intent, inaccurate constraints, and other factors that lead to noise. A new Aldec webinar offers guidance to improve CDC results.
Sergei Zaychenko of Aldec offers one diagram as a refresher on how CDCs create metastability, and the variables that factor into MTBF. His “impossible to avoid” comment – if there are multiple clock domains, there are CDCs by definition – suggests the urgency of finding and mitigating CDCs in an FPGA design.
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