by Don Dingee
Multiple clock domains in FPGAs have simplified some aspects of designs, allowing effective partitioning of logic. As FPGA architectures get more flexible in how clock domains, regions, or networks are available, the probability of signals crossing clock domains has gone way up.
We know one result: metastability, where a signal crossing two domains with differing clock sources in an unknown relationship results in an indeterminate state. And, we know one way to fix that, at least generally: a couple layers of registering or flip-flops.
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