Aldec™ Design and Verification Newsletter: Q1, 2013
2012: Emulation's Big Year, and a Look Ahead to 2013
Camouflage for Your HDL Code
2012 was an exceptional year for Aldec globally. The company exceeded revenue expectations across all product offerings, the most significant changes coming from Emulation. Aldec continued to see double digit growth in our traditional market areas of FPGA and ASIC HDL Verification (Active-HDL™, Riviera-PRO™) and Design Analysis and Rule Checking (ALINT™). 2012 also brought several successful and strategic account wins in DO-254, RTAX Prototyping adapters, Hardware-Assisted Verification (HES-DVM™) and the shipment of our first HES-7™ ASIC prototyping platforms based on Xilinx® Virtex®-7 2000T.
Aldec attributes its success to one simple-yet-obvious formula: listen to the customer then relentlessly strive to meet their real-world needs by delivering award-winning solutions. This explains how Aldec is able to continually serve up innovative products that leverage time-saving methodologies, and is poised to continue to grow as we approach our 30 year anniversary in 2014.
Keep your eye on Aldec in 2013 as we introduce new products while continuing to deliver innovative enhancements to our existing solutions - all designed to meet our customer's real-world requirements.
Time and effort spent on FPGA debug and verification is already considerably high and only increasing. The complexity of today's FPGA device has increasingly grown, the size of designs making it challenging to leverage the in-hardware testing approach. At the same time, fierce competition is shrinking time-to-market requirements. This makes it difficult for designers to use the legacy approach of implement-and-test designs in hardware. While most FPGA vendor tools provide solutions for basic simulation to adequately support their low density devices, these tools lack the powerful debugging and verification needed to allow designers to be competitive in meeting schedules and efficiently debugging large scale FPGAs. Read More
Aldec has recently added tools to explore dataflow and connectivity in FPGA designs, including X-value detector and Code Coverage to enable FPGA designs a comprehensive debugging environment.
X-Trace. Monitoring unknown values during simulation is a time challenging task, especially when simulation runs for an extended amount of time.In a typical scenario, any unknown values that appear during the simulation will propagate through the design and will be visible at the end of the simulation. This in turn requires designers to trace back to the source of the issue, a time-consuming task as unknown values may have propagated deep down in the hierarchy. X-Trace is the debugging tool that allows designers to detect and report unknown values right when they appear during simulation. It reports unexpected values, signals and the time when those values were detected, providing designer more time to fix the actual issue rather than searching for it.
Advanced Dataflow is a useful graphical debugging tool that identifies an unexpected output by graphically tracing the events that may have propagated through design. It is often used to debug the design during simulation for tracing signal values and exploring the physical connectivity of the design.
Code Coverage tools for metric based verification, which is required by most verification plans, are very common in today's FPGA design development flow.
Code coverage measures how much code is checked by the testbench, providing information about dead code in the design and holes in test suits. Code coverage also helps improve the predictability and quality of the test environment. Popular code coverage types that are used by designers around the world include Statement/Branch Coverage, Expression/Condition Coverage and Path Coverage.
Active-HDL has now enabled all of these features in its Plus Edition configuration at no cost. Current Active-HDL users are encouraged to obtain an updated license to take advantage of these powerful debugging features.
Designers may deliberately obfuscate HDL code to conceal its purpose (security through obscurity) or its logic, in order to prevent tampering and deter reverse engineering. The obfuscated code is unreadable to the receiving user, but is still readable to compilers and simulators. This way obfuscation also comes in handy when you need to share your source code with an EDA tool vendor for debugging and don't want the recipient to see the contents of the actual file. Aldec provides the script to obfuscate VHDL, Verilog, and SystemVerilog code.
For steps to execute this script, see related App Note, HDL Code Obfuscation.
Aldec's interactive training portal, Fast Track ONLINE™, is coming soon and will be available at no cost to all aldec.com registered users. Fast Track ONLINE™ trainings are made up of several modules, making it easy for engineers to learn at their own pace. Private, online trainings will allow the user to go back to review material, and each individual module ends with quick self-test before proceeding to ensure the module is grasped before proceeding. Read More
The premiere training course, 'Fast Track to UVM ONLINE', introduces hardware designers familiar with Design Subset of SystemVerilog to the brave, new world of Universal Verification Methodology (UVM). Tool Trainings, Assertions and other exciting topics will follow.
All registered users of Aldec.com will receive email notification when Fast Track ONLINE™ Training portal is launched in February. Don't have an account? Signing up is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources.
The Tasks window in Riviera-PRO and ALINT can be used to manage tasks that need to be completed in the design. Tasks can be anything that a user would like to address later in the project. In a team-based environment where multiple engineers are working with different aspects of the same design, it is difficult to coordinate tasks among different engineers. This becomes even more difficult when a team is working on one tool to create the design, and a team lead is using another tool to do the code review and design rule checking. For step-by-step details see related App Note, Interoperability of Project tasks between Riviera-PRO and ALINT.
Robustness testing is required for DO-254 DALs A and B. The purpose of robustness testing is to demonstrate that the device functions as intended - not only under normal operating conditions but also under abnormal operating conditions. Requirements-based tests usually cover test cases for normal conditions, but do not cover test cases for abnormal conditions. This is why applicants are expected to add robustness test cases to the verification plans to ensure the device functions as intended under all foreseeable conditions. Read More
Examples of industry best-practice robustness tests include the following:
Aldec, Inc., announced enhancement of the HES™-7 FPGA-based prototyping platform with ARM dual-core Cortex™-A9 MPCore Microprocessor implemented with Xilinx® Zynq™ All Programmable SoC. The release furthermore provides users many essential peripherals (media interfaces, memories, and connectors) for added flexibility in developing a wide array of SoC applications. Partnering the HES-7 Prototyping Platform with free open-source Linux, Android, and FreeRTOS solutions from Xilinx, opens an easy and affordable path for software developers of ARM Cortex applications. Read More
Designers can now leverage the serial processing capabilities of the Cortex-A9 processor for applications that require intensive computations and operating systems with the parallel processing capabilities of HES-7 ASIC prototyping platform to create applications across a diverse range of markets including: Video, Communications, Control Systems and Bridging.
Prototyping with the Powerful HES-7
Riviera-PRO provides a bidirectional MATLAB co-simulation interface that allows the integration of the MathWorks' system-level computing environment with Aldec's HDL-based simulation environment. The interface enables engineers to verify that their ASIC/FPGA implementations match system specifications. Riviera-PRO can either act as a master or slave in co-simulation with MATLAB. Read More
Slave mode enables MATLAB users to play with a bit-accurate model of their IP without even having to leave the MATLAB environment. Riviera-PRO's MATLAB interface supports the flow in which you can keep MATLAB as a main environment and can call Riviera-PRO for HDL simulations. This way, you may not even need to deal with the HDL simulation environment at all (given your design-specific interface implemented by someone else at the HDL side).
For step-by-step details see related App Note: Controlling Riviera-PRO from MATLAB®.
SystemVerilog introduced numerous ideas new to Verilog programmers. Some of them enhanced hardware descriptions (e.g. always_ff block), some were meant to enhance verification (e.g. classes) and some were cross-over enhancements that can be used in many different contexts. SystemVerilog interface construct belongs to the cross-over group: it offers useful features for both hardware designers and verification engineers. The unfortunate side effect of this variety of applications is the confusion among SV users: all of them heard about interfaces, many used them to some extent, but virtually nobody fully mastered them.
To learn more, read our White Paper: Those Pesky SystemVerilog Interfaces
Recorded Webinar: Best Design Practices for High-Capacity FPGA Devices
ALINT is an easy-to-use yet advanced Verilog/VHDL design rule checker (DRC) tool by Aldec. It identifies critical coding style, functional, and structural problems early in ASIC/FPGA design cycle by checking your RTL description against hundreds of "best practice" RTL design rules. ALINT's extensive rule libraries are based on proven design guidelines, such as STARC and RMM, that have been established over the years by industry-leading companies in FPGA and ASIC design development. Read More
These getting started guides are intended for users with no previous experience with ALINT DRC/linting tool. They introduce you with the basic flow how to set up the linting environment, prepare a custom policy, run design linting checks, and analyze the results.
1. Creating and Customizing Design Policies
2. Creating and Linting a Design in ALINT
3. Creating a Script for Batch-Mode Linting
Linting technology may uncover a variety of hidden bugs at the right time, when cost and efficiency of modifications are optimal, and highly reduce the risks of redundant design iterations and costly re-spins.
Aldec's YouTube Featured Video: HES-7™ 7-Series FPGA Programming
The 7-Series FPGA devices on Aldec's ASIC prototyping platform can be programmed using two different methods: using a standard Xilinx Platform Cable with Xilinx's impact programming tool or using a USB interface with Aldec's hes7proto application. This video provides step-by-step instruction on how to perform both methods, along with a description of the cables and necessary material needed to program the 7-Series FPGAs.
YouTube Video: HES-7™ 7-Series FPGA Programming
Subscribe to AldecInc on YouTube for the latest videos on a variety of design and verification topics along with product demonstration videos.
The latest release of Active-HDL introduces advanced features to boost productivity. Active-HDL 9.2 introduces the powerful concept of Flexible File Management to simplify FPGA project management by allowing customization and the ability to create common project structure across multiple vendor tools.
Major features that are included in Active-HDL 9.2 are:
User-defined Design Management – Customize directory structure to fit project environment. No need to use directory structure across multiple vendor tools.
Mouse Strokes - Perform common tasks with simple mouse movements.
Multiple symbols for same library unit - generate multiple variances of a symbol for the same VHDL entity or Verilog module. Create different shape and color symbols for the same library unit.
Route optimization for schematics – Automatically optimize and reduce redundant net segment on schematics.
Annotate Waveform – Place message balloons on waveform for enhanced debugging and documentation.
Support for latest FPGA device – Design flow manager updated to support latest vendor tools and libraries
New Features and Enhancements: Active-HDL 9.2 Release Notes
What's New Presentation: What's New in Active-HDL 9.2
Aldec recently announced the release of its mixed language advanced verification platform, Riviera-PRO™ 2012.10. The release delivered numerous stability and performance improvements, support for the latest versions of industry-standard SystemVerilog verification libraries, new language constructs, new debugging tools, and improved interfaces to other industry leading EDA tools.
Highlights of Riviera-PRO 2012.10:
Core Simulation Engine
Framework and Productivity
3rd Party Interfaces
"What's New" presentation: Riviera-PRO 2012.10 What's New
Complete list of new features and enhancements Riviera-PRO 2012.10 Release Notes
Related press release: Aldec Boosts VHDL Simulation Performance
ALINT™ 2012.12 is an advanced static design analysis and checking solution that decreases verification time by identifying critical issues early in the RTL design phase of ASIC and FPGA designs. The release delivered performance improvements, a team-based task management utility, and a new premium rule library that included checkers to optimize routing resources in designs targeting today's largest FPGAs.
Highlights of ALINT 2012.12:
"What's New" presentation: ALINT 2012.12 What's New
Complete list of new features and enhancements: ALINT 2012.12 Release Notes
Related press release: Aldec Optimizes FPGA Routing Resources for Power and Performance
HES-DVM™ is a complete ASIC/SoC hardware-based verification solution that provides a unified platform for bit level simulation acceleration, transaction level emulation, system architecture exploration, HW/SW co-verification, virtual modeling and ASIC prototyping.
New Features and updates:
SCE-MI 2.0 Compiler Now Supports:
Easy Hardware Clock Connection for Speed-Bridge with complete integration from within the emulation setup mode. Connects at any hierarchy level and automatically generates implementation constraints for hardware clocks.
4x speed improvement in SystemC co-simulation over previous release. Added static debug probes for support of bits and vectors.
Aldec recently unveiled HES-7™, a scalable, high quality FPGA-based ASIC prototyping solution for SoC/ASIC hardware verification and software validation teams backed by an industry leading 1-Year warranty.
Top Features and Benefits of HES-7 include:
Prototyping with HES-7
Support for Xilinx Zynq
Essential SoC Peripherals Included