Aldec™ Design and Verification Newsletter: Q1, 2013

Date: Jan 29, 2013Type: Newsletter


2012: Emulation's Big Year, and a Look Ahead to 2013
Simplify your FPGA Verification: New Tools for Comprehensive Debugging
'Fast Track to UVM' Interactive Online Training - Coming in February
Robustness Testing for DO-254 Designs
Aldec Adds HES-7 Prototyping Platform with Support for ARM® Cortex Microprocessor


Camouflage for Your HDL Code
Interoperability of Project Tasks between Riviera-PRO and ALINT
Controlling Riviera-PRO from MATLAB®
Those Pesky SystemVerilog Interfaces…
Best Design Practices for High-Capacity FPGA Devices
Become a Linting Expert in 3 Easy Steps
HES-7™ 7-Series FPGA Programming

2012: Emulation's Big Year, and a Look Ahead to 2013

Dr Stanley Hyduke Aldec President and CEO

2012 was an exceptional year for Aldec globally. The company exceeded revenue expectations across all product offerings, the most significant changes coming from Emulation. Aldec continued to see double digit growth in our traditional market areas of FPGA and ASIC HDL Verification (Active-HDL™, Riviera-PRO™) and Design Analysis and Rule Checking (ALINT™). 2012 also brought several successful and strategic account wins in DO-254, RTAX Prototyping adapters, Hardware-Assisted Verification (HES-DVM™) and the shipment of our first HES-7™ ASIC prototyping platforms based on Xilinx® Virtex®-7 2000T.

Aldec attributes its success to one simple-yet-obvious formula: listen to the customer then relentlessly strive to meet their real-world needs by delivering award-winning solutions. This explains how Aldec is able to continually serve up innovative products that leverage time-saving methodologies, and is poised to continue to grow as we approach our 30 year anniversary in 2014.

Keep your eye on Aldec in 2013 as we introduce new products while continuing to deliver innovative enhancements to our existing solutions - all designed to meet our customer's real-world requirements.

Simplify your FPGA Verification: New Tools for Comprehensive Debugging

Comprehensive Debugging

Time and effort spent on FPGA debug and verification is already considerably high and only increasing. The complexity of today's FPGA device has increasingly grown, the size of designs making it challenging to leverage the in-hardware testing approach. At the same time, fierce competition is shrinking time-to-market requirements. This makes it difficult for designers to use the legacy approach of implement-and-test designs in hardware. While most FPGA vendor tools provide solutions for basic simulation to adequately support their low density devices, these tools lack the powerful debugging and verification needed to allow designers to be competitive in meeting schedules and efficiently debugging large scale FPGAs. Read More

Camouflage for Your HDL Code

Camouflage VHDL

Designers may deliberately obfuscate HDL code to conceal its purpose (security through obscurity) or its logic, in order to prevent tampering and deter reverse engineering. The obfuscated code is unreadable to the receiving user, but is still readable to compilers and simulators. This way obfuscation also comes in handy when you need to share your source code with an EDA tool vendor for debugging and don't want the recipient to see the contents of the actual file. Aldec provides the script to obfuscate VHDL, Verilog, and SystemVerilog code.

For steps to execute this script, see related App Note, HDL Code Obfuscation.

'Fast Track to UVM' Interactive Online Training - Coming in February

Fast Track Interactive Online TrainingAldec's interactive training portal, Fast Track ONLINE™, is coming soon and will be available at no cost to all aldec.com registered users. Fast Track ONLINE™ trainings are made up of several modules, making it easy for engineers to learn at their own pace. Private, online trainings will allow the user to go back to review material, and each individual module ends with quick self-test before proceeding to ensure the module is grasped before proceeding. Read More

Interoperability of Project Tasks between Riviera-PRO and ALINT

Interoperability Of Project Tasks

The Tasks window in Riviera-PRO and ALINT can be used to manage tasks that need to be completed in the design. Tasks can be anything that a user would like to address later in the project. In a team-based environment where multiple engineers are working with different aspects of the same design, it is difficult to coordinate tasks among different engineers. This becomes even more difficult when a team is working on one tool to create the design, and a team lead is using another tool to do the code review and design rule checking. For step-by-step details see related App Note, Interoperability of Project tasks between Riviera-PRO and ALINT.

Robustness Testing for DO-254 Designs

DO-254Robustness testing is required for DO-254 DALs A and B. The purpose of robustness testing is to demonstrate that the device functions as intended - not only under normal operating conditions but also under abnormal operating conditions. Requirements-based tests usually cover test cases for normal conditions, but do not cover test cases for abnormal conditions. This is why applicants are expected to add robustness test cases to the verification plans to ensure the device functions as intended under all foreseeable conditions. Read More

Aldec Adds HES-7 Prototyping Platform with Support for ARM® Cortex Microprocessor

HES-7Aldec, Inc., announced enhancement of the HES™-7 FPGA-based prototyping platform with ARM dual-core Cortex™-A9 MPCore Microprocessor implemented with Xilinx® Zynq™ All Programmable SoC. The release furthermore provides users many essential peripherals (media interfaces, memories, and connectors) for added flexibility in developing a wide array of SoC applications. Partnering the HES-7 Prototyping Platform with free open-source Linux, Android, and FreeRTOS solutions from Xilinx, opens an easy and affordable path for software developers of ARM Cortex applications. Read More

Controlling Riviera-PRO from MATLAB®

MATLABRiviera-PRO provides a bidirectional MATLAB co-simulation interface that allows the integration of the MathWorks' system-level computing environment with Aldec's HDL-based simulation environment. The interface enables engineers to verify that their ASIC/FPGA implementations match system specifications. Riviera-PRO can either act as a master or slave in co-simulation with MATLAB. Read More

Those Pesky SystemVerilog Interfaces...

Good Luck

SystemVerilog introduced numerous ideas new to Verilog programmers. Some of them enhanced hardware descriptions (e.g. always_ff block), some were meant to enhance verification (e.g. classes) and some were cross-over enhancements that can be used in many different contexts. SystemVerilog interface construct belongs to the cross-over group: it offers useful features for both hardware designers and verification engineers. The unfortunate side effect of this variety of applications is the confusion among SV users: all of them heard about interfaces, many used them to some extent, but virtually nobody fully mastered them.


To learn more, read our White Paper: Those Pesky SystemVerilog Interfaces

Best Design Practices for High-Capacity FPGA Devices

With the latest FPGA technology advancements and release of high capacity devices such as Xilinx® Virtex®-7 and Altera® Stratix®-V, design teams face more challenges producing safe and clean HDL (RTL, FPGA) code. In this webinar, we focus on the design techniques that will result in the code running most optimally on the large FPGA designs, and be free of timing and synchronization issues.

Recorded Webinar: Best Design Practices for High-Capacity FPGA Devices

Become a Linting Expert in 3 Easy Steps!

ALINT Become An Expert

ALINT is an easy-to-use yet advanced Verilog/VHDL design rule checker (DRC) tool by Aldec. It identifies critical coding style, functional, and structural problems early in ASIC/FPGA design cycle by checking your RTL description against hundreds of "best practice" RTL design rules. ALINT's extensive rule libraries are based on proven design guidelines, such as STARC and RMM, that have been established over the years by industry-leading companies in FPGA and ASIC design development. Read More

Aldec's YouTube Featured Video: HES-7™ 7-Series FPGA Programming

Aldec YouTube ChannelThe 7-Series FPGA devices on Aldec's ASIC prototyping platform can be programmed using two different methods: using a standard Xilinx Platform Cable with Xilinx's impact programming tool or using a USB interface with Aldec's hes7proto application. This video provides step-by-step instruction on how to perform both methods, along with a description of the cables and necessary material needed to program the 7-Series FPGAs.

YouTube Video: HES-7™ 7-Series FPGA Programming

Subscribe to AldecInc on YouTube for the latest videos on a variety of design and verification topics along with product demonstration videos.

Product Updates

Active-HDL™ 9.2

The latest release of Active-HDL introduces advanced features to boost productivity. Active-HDL 9.2 introduces the powerful concept of Flexible File Management to simplify FPGA project management by allowing customization and the ability to create common project structure across multiple vendor tools.


Major features that are included in Active-HDL 9.2 are:

User-defined Design Management – Customize directory structure to fit project environment. No need to use directory structure across multiple vendor tools.

Mouse Strokes - Perform common tasks with simple mouse movements.

Multiple symbols for same library unit - generate multiple variances of a symbol for the same VHDL entity or Verilog module. Create different shape and color symbols for the same library unit.

Route optimization for schematics – Automatically optimize and reduce redundant net segment on schematics.

Annotate Waveform – Place message balloons on waveform for enhanced debugging and documentation.

Support for latest FPGA device – Design flow manager updated to support latest vendor tools and libraries

New Features and Enhancements: Active-HDL 9.2 Release Notes

What's New Presentation: What's New in Active-HDL 9.2


Riviera-PRO™ 2012.10 

Aldec recently announced the release of its mixed language advanced verification platform, Riviera-PRO™ 2012.10. The release delivered numerous stability and performance improvements, support for the latest versions of industry-standard SystemVerilog verification libraries, new language constructs, new debugging tools, and improved interfaces to other industry leading EDA tools.


Highlights of Riviera-PRO 2012.10:


Core Simulation Engine

  • Simulation performance improvements - VHDL simulation now up to 20% faster!
  • New language constructs in SystemVerilog'2009 and VHDL'2008
  • Support for the latest verification libraries - UVM 1.1c, SystemC 2.3.0, OS-VVM™
  • Increase Stability on large multi-million gate designs

Framework and Productivity

  • Waveform enhanced for displaying of composite objects (virtual arrays)
  • Possibility to rename objects in the waveform, and context search
  • Additional operations using the drag-n-drop method

3rd Party Interfaces

  • The new way to use MATLAB co-simulation interface - Invoke Riviera-PRO from MATLAB
  • The latest precompiled simulation libraries for Altera and Xilinx FPGAs
  • Compatibility with the latest release of Xilinx Vivado™ Design Suite supporting Virtex-7
  • FSDB updated to the version 5.0 - Compatible with Verdi3 2012.07


"What's New" presentationRiviera-PRO 2012.10 What's New

Complete list of new features and enhancements Riviera-PRO 2012.10 Release Notes

Related press release: Aldec Boosts VHDL Simulation Performance

ALINT 2012.12™

ALINT™ 2012.12 is an advanced static design analysis and checking solution that decreases verification time by identifying critical issues early in the RTL design phase of ASIC and FPGA designs. The release delivered performance improvements, a team-based task management utility, and a new premium rule library that included checkers to optimize routing resources in designs targeting today's largest FPGAs.


Highlights of ALINT 2012.12:

  • New Aldec Premium rule library with routing-aware rules for large scale FPGAs
  • Project task management integrated with Aldec Riviera-PRO
  • STARC Design Style Guides in Japanese Kanji and English
  • Automatic code analysis (on-the-fly syntax checks)
  • Advanced variable-based HDL coding templates
  • Precompiled FPGA vendor libraries for latest devices
  • Over 40 important bug fixes and performance improvements


"What's New" presentationALINT 2012.12 What's New

Complete list of new features and enhancements: ALINT 2012.12 Release Notes

Related press release: Aldec Optimizes FPGA Routing Resources for Power and Performance



HES-DVM™ is a complete ASIC/SoC hardware-based verification solution that provides a unified platform for bit level simulation acceleration, transaction level emulation, system architecture exploration, HW/SW co-verification, virtual modeling and ASIC prototyping.

New Features and updates:

SCE-MI 2.0 Compiler Now Supports:
- Shared registers are converted from multi-source assignments into merged logic that is synthesizable allowing for easier coding of transactors.
- Implicit State Machines for easier coding of SCE-MI transactors, no need to maintain explicit state registers and is faster to adopt by Verification Engineers.
- Messages Streaming is optimized for speed to improve co-emulation runtime speeds. It supports a non-blocking message transport and data streams that do not require delivery confirmation.

Easy Hardware Clock Connection for Speed-Bridge with complete integration from within the emulation setup mode. Connects at any hierarchy level and automatically generates implementation constraints for hardware clocks.

4x speed improvement in SystemC co-simulation over previous release. Added static debug probes for support of bits and vectors.



Aldec recently unveiled HES-7™, a scalable, high quality FPGA-based ASIC prototyping solution for SoC/ASIC hardware verification and software validation teams backed by an industry leading 1-Year warranty.


Top Features and Benefits of HES-7 include:


Prototyping with HES-7

  • Available in a scalable capacity from 4 to 96 million ASIC gates
  • Single and Dual FPGA Configurations Reduce Complex Partitioning
  • Non-Proprietary daughterboard connectors
  • Superior Quality Backed by Industry Leading 1-Year Warranty
  • Lowers Cost of Overall ASIC Prototype Process


Support for Xilinx Zynq

  • Utilize ARM dual-core Cortex-A9 MPCore Microprocessor
    • Maximum Frequency of up to 1 GHz
    • Enhanced with NEON Extension and Single & Double Precision Floating point unit
    • 32 kB Instruction & 32 Data kB L1 Cache
  • Integrated processing platform with FPGA logic reduces bill-of-material (BOM) up to 40
  • Free open-source Linux, Android, and FreeRTOS solutions available from Xilinx


Essential SoC Peripherals Included

  • Media Interfaces – Ethernet PHY 10/100/1000, Wi-Fi and Bluetooth, USB 2.0 DEVICE, USB 2.0 HOST, USB 2.0 OTG, HDMI, and Audio Codec (Stereo Speaker and MIC Interfaces)
  • Memories –  SD Socket, SPI Flash, I2C Flash, NAND Flash, SO-DIMM DDR2
  • Connectors – ARM Debug, RS232, I2C, SPI, and GPIO
  • Additional 4x DDR3 Memory peripheral included with Xilinx Zynq



  • FPGA Design & Verification
  • Graphical Design Entry
  • Mixed-Language Simulator
  • Code Coverage Tools
  • MATLAB®/Simulink® Interface
  • HTML & PDF Documentation 


  • Advanced Verification Platform (OVM/UVM, VMM)
  • IEEE Std. Compliant High-Performance Simulator
  • Assertion-Based Verification (SVA, PSL, OVA)
  • Code and Functional Coverage
  • Powerful IDE, Tcl scripting
  • Co-Simulation with DSP and RF Tools
  • Linux and Windows 32/64-Bit


  • Early bugs detection (RTL)
  • Industry-proven design guidelines
  • Guided design refinement (PBL)
  • In-house design expertise automation
  • IDE for in-depth design troubleshooting
  • VHDL, Verilog®, mixed-language
  • C++ based API (custom rules)


  • 7MHz Emulation Speed, 37 Million ASIC Gates
  • SCE-MI 2.0 DPI-C Support
  • Integration with Riviera-PRO: Adding/Removing Debugging Signals and Emulation Start/Stop/Step
  • Dynamic Triggers - Flexible Probes


  • Scalable Capacity From 4 - 96 million ASIC Gates
  • Easy To Use with Reduced Design Partitioning
  • Expandable via Non-Proprietary Connector
  • ARM® Cortex™ Support with Xilinx® Zynq™
  • SoC Peripherals: Media Interfaces, Memories, and Connectors
  • Supports Linux, Android, and FreeRTOS

Did You Know?

You can start Riviera-PRO™ as a default simulator in Xilinx® Vivado® to run behavioral and timing simulations. See app note for details.

ALINT™ has a unique "native support" for designs that use simulation libraries from Xilinx® and Altera®, making linting reports more accurate; this app note explains how it works.

In Active-HDL™ you can convert standard waveform file (*.awf) to accelerated waveform file (*.asdb) by just right clicking on standard waveform file and choosing and option “Convert to Accelerated Waveform (ASDB)” in GUI or by using awf2asdb command.

You can perform automatic grouping of VHDL or Verilog syntax in Active-HDL™ by right clicking in the HDL editor and selecting Document Structure | Generate Structure. This feature can be completely customized from the Tools | Preferences | Editor | HDL Editor | Languages to allow users to choose which VHDL and Verilog constructs to be grouped and which colors to be assigned to different groups.  

Customers can build their own customer daughter boards to interface with the HES-7™. See Tech Spec for info such as connectors, mapping tables, power sequence, etc. to get started.



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