Henderson, NV - January 2, 2013 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, today announced that Taiwan National Chiao Tung University has adopted Aldec’s emulation and verification tools for their new and innovative Master of Advanced Studies (MAS) Program in ESL Design. To provide the master’s program with world class commercial EDA products, Aldec will provide licenses for Riviera-PRO™ mixed-language simulation and verification platform and HES-EDU™ hardware-assisted verification.
“Aldec is committed to education and we believe in the importance of educating both working and future engineers in leading-edge verification methodologies and tools,” said Dick Tao, Aldec Taiwan Country Manager, “For this reason Aldec is proud to invest in the success of this program by providing students with access to our latest tools.”
“The MAS Program in ESL Design allows professional engineers to take advantage of National Chiao Tung University world-renowned expertise in intelligent vision system & SoC design methodology,” said professor Jiun-In Guo, Graduate School Director of Electronics Engineering Department, National Chiao Tung University at Taiwan, “This program provides the students a unique opportunity to build complete, state-of-the-art ESL systems using advanced commercial tools and we consider Aldec design tools as integral to our program.”
“A model for master’s degrees in engineering, this program offers intense hands-on experience and training for the engineering talent of tomorrow in advanced laboratories with substantial guidance from working engineers,” added professor Jiun-In Guo. “We are grateful to Aldec, Andestech, Xilinx, and other companies for making such labs possible.”
About NCTU’s ESL Design Master’s Program
The NCTU School of Engineering recently launched an innovative new master’s degree program tailored to the needs of industry and engineering professionals. The MAS program in ESL Design allows students to gain a deep and broad education in the multidisciplinary fundamentals of image processing design and ESL Design. http://www.ee.nctu.edu.tw/
HES is a complete ASIC/SoC hardware-based verification solution from Aldec that provides a unified platform for bit level simulation acceleration, transaction level emulation, system architecture exploration, HW/SW co-verification, virtual modeling and prototyping.
The Design Verification Manager (HES-DVM™) is the main software of HES facilitating easy design setup and flexibility with its fully scriptable environment, ASIC to FPGA clock conversion, automatic design partitioning, advanced HDL compiler, incremental compilation and interface with commercial simulators. www.aldec.com/products/hes-dvm
Riviera-PRO is a multi-platform, high-performance, mixed-language RTL and gate-level simulator for ASIC and FPGA designs. Riviera-PRO includes advanced debugging tools and support of advanced verification methodologies with SystemC and SystemVerilog, Assertions Based Verification (ABV), Transaction Level Modeling (TLM) and VHDL/Verilog Design Rule Checking. www.aldec.com/products/riviera-pro
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, ASIC Prototyping, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
|Media Contact:||Christina Toole,