Q4-2012 - Aldec™ Design and Verification Newsletter
Improve Productivity with User-Defined Design Management
Working with today's complex FPGA projects involves dealing with many different types of HDL files, IPs, libraries, schematics, waveforms etc. Every engineer must juggle these files many times during the FPGA design development phase, and it is critical that FPGA design tools allow users to define and organize the structure of the FPGA project based on user needs. Read More
Having the freedom to create user-defined project structures dramatically improves collaboration and productivity.
Mice. These ubiquitous yet powerful devices can increase user productivity when used efficiently. Mouse Strokes allow users to perform common and repetitive tasks with simple mouse movements. This is especially convenient when using today’s popular dual or multiple screens that require a fair amount of mouse movement - particularly when using tools menus. Read More
Mouse strokes allow users to perform different operations anywhere on the screen without accessing the menus.
This unintimidating webinar will begin with a solid review of SystemVerilog interfaces with special attention paid to those mysterious Virtual Interfaces, proceeding to Sequences and other Data Items, processed by Sequencers and fed to the design under test via Drivers. The role of Monitors and Scoreboards in analysis of results is also explained. Read More
The presentation concludes with environment configuration and running test from the top-level module.
Attendees not familiar with Object Oriented Programming (OOP) and Transaction-Level Modeling (TLM) are strongly encouraged to view our previously recorded webinars: "Know Your Objects - OOP for Hardware Designers" and "TLM Concepts for Hardware Designers".
Visit www.aldec.com/events for additional information about upcoming Aldec events.
Aldec recently released HES-7™, a scalable prototyping board that allows designers the ability to verify ASIC/SoC designs up to 24 million gates. HES-7 utilizes new Xilinx® Virtex®-7 FPGAs which implement Stacked Silicon Read More
Interconnect technology (SSI), making them the industry’s largest capacity FPGAs available. With non-proprietary backplane/daughter board connectors HES-7 can attach up to (4) HES-7 boards allowing up to 96M gate capacity, or allow designers the ability to use their own pre-existing daughter boards for an array of application uses. The HES-7 comes with single or dual FPGA configurations which eliminate complex design partitioning issues, allowing companies to verify their design more quickly and reduce the time-to-market time frame. This reduces overall development cost, and increases profit margin by eliminating the need for re-spins after tape-out.
For Technical Specifications and additional information about the HES-7 prototype system, visit www.aldec.com/products/HES-7
Related white paper: ASIC Prototyping (co-authored with Xilinx)
Aldec's newly released FPGA-based prototyping platform, HES-7™, leverages Xilinx® Virtex®-7 FPGA. Read More
Xilinx has introduced a new Stacked Silicon Interconnect technology (SSI), enabling a single Virtex-7 to have 2M logic cells, making it the industry’s largest capacity FPGA. This webinar will provide an overview of modifications to previous Xilinx architecture and the structuring of SSI technology. The webinar will also present how the Virtex-7 benefits FPGA-based prototyping platforms, and will also provide an overview of HES-7 key features.
The system reset carries out a critical function of forcing the SoC into a predictable state. Depending on what's appropriate for SoC's target application, the designer may use the Asynchronous or Synchronous reset method, or even a combination of the two.
Every reset method comes with its own advantages and disadvantages. However Asynchronous resets are a little more challenging to handle as they require certain effort during the RTL design phase. Using the reset synchronizer logic is a common design practice that helps to avoid metastability. As shown in Figure 2, an external reset signal asynchronously resets a pair of flip-flops which drive the master reset to the rest of flip-flops in the design (so that the design is synchronously reset).
With synchronization circuit like this, it takes two clock edges to synchronize removal of the master reset. The reset active state of reset signal is asserted asynchronously and released synchronously with the clock.
Following the sample timing diagram in Figure 3, let's review an example of how the synchronizer mitigated a metastable condition:
To help you make sure that resets are handled properly in your design, Aldec’s ALINT™ features an array of rules that automatically recognize global reset, internally generated resets, reset synchronization circuits, and provide early recommendations on design structure, with particular focus on clock and reset lines in your design. Here are some examples of 20+ reset-related rules available with ALINT:
Request a free evaluation today to test drive ALINT with your current design.
As described in DO-254, any inability to verify specific requirements by test on the device itself must be justified and alternative means of verification provided. Certification authorities favor verification by test for formal verification because of the simple fact that hardware flies, not simulation models. Requirements describing FPGA pin level behavior must be verified by test. Read More
The problem is that testing the FPGA device at the board level provides very low FPGA input control, thus making it difficult to inject certain signals for normal range tests and robustness tests.
Below is a list of recommendations that can be implemented to increase verification coverage by test. The list of recommendations proposes a methodology that can leverage the same test cases and test inputs for simulation and device testing allowing for a much stronger argument of verification fidelity and validity to the certification authority.
Aldec's DO-254/CTS™ can help facilitate the recommendations provided here. DO-254/CTS can leverage the same test cases and test inputs from simulation during device testing. Test vectors can be generated during functional simulation and reused as test inputs for device testing. DO-254/CTS provides 100% FPGA input control and outputs access points so that requirements are easily verifiable by test for normal range and robustness tests. DO-254/CTS consists of custom hardware specific to the target device and design utilizing real clocks to enable at-speed testing.
For more information about DO-254/CTS, visit www.aldec.com/do254.
Aldec/Altera Joint DO-254 Webinar: How to Increase Verification Coverage by Test
As cloud based services become more popular and efficient, it raises the question: Is cloud the right way to go for me? The answer depends on what you are planning to achieve by using the cloud. Read More
There are a few questions you need to answer before deciding if you want to use the cloud services:
If you answered yes to any of the above questions, then cloud based simulation might benefit you. Aldec Cloud enables the user to launch multiple nodes at one time, and enables running testcases in parallel - rather than one after the other. Both UI and hardware infrastructure on Aldec Cloud are setup and ready to go, making it very easy to start running simulation jobs. Overall testing or regression time can be significantly reduced depending on the user's test suite. Since the price model for Aldec Cloud is based on per hour usage, it can be utilize it for peak needs and without the worry of paying for simulator licenses.
Now, that we've determined that cloud based simulation might be a useful resource for your needs, consider these Do's and Dont's to make the process more efficient:
To learn more or to register for a free trial, visit www.aldec.com/cloud.
Tools like Xilinx® Vivado™ HLS and NEC CyberWorkBench enable an alternative approach to the traditional IC design methodology by providing algorithmic (rather than typical hardware) development environment. Instead of manually creating a register-transfer-level (RTL) implementation, designers can cut development time by orders of magnitude by representing their algorithms at a higher level of abstraction (C, C++, or SystemC) and verifying reference system behavior at the same level of abstraction. Read More
Fortunately, the C testbench can be reused to perform RTL verification, saving enormous amount of time usually spent for traditional verification at this level of abstraction. Aldec Riviera-PRO™ enables automatic C testbench reuse for the RTL simulation, and provides complimentary technologies such as code coverage and profiling tools, making it easier to verify the RTL descriptions synthesized based on C-based languages. And using HES-7™, Aldec's new prototyping platform with largest Xilinx Virtex®-7 devices onboard, users can target their high-level specifications directly into FPGA for execution in real time.
Today's FPGA designer is faced with many design challenges created from the increased time to market demands and complexities of their design. With the added external demands stemming from employee turnover and the proprietary nature of designs, Active-HDL offers the needed flexibility for organizations confronted with the development of programmable logic designs. Read More
Potential Challenges faced by companies and their designers:
For more on these challenges and possible solutions, see related white paper: Corporate Standardization of FPGA Design Flow.
The Waveform Viewer window is an essential debugging tool that allows you to view the results of your simulation as timing waveforms. The Viewer allows you to see the signal transitions over time and relation of those signals with other signals in a design, zoom in and out over a time sequence, take measurements between Read More
two cursor points, and perform many other operations to comprehend and debug your design.
Riviera-PRO's Waveform Viewer is packed with features. To help ensure you are using the tool in the most productive ways, we have compiled a list of videos on the most basic yet essential aspects of the Waveform Viewer tool:
Subscribe to AldecInc on YouTube for the latest videos on a variety of design and verification topics along with product demonstration videos.
The latest release of Active-HDL introduces advanced features to boost productivity. Active-HDL 9.2 introduces the powerful concept of Flexible File Management to simplify FPGA project management by allowing customization and the ability to create common project structure across multiple vendor tools.
Major features that are included in Active-HDL 9.2 are:
User-defined Design Management - Customize directory structure to fit project environment. No need to use directory structure across multiple vendor tools.
Mouse Strokes – Perform common tasks with simple mouse movements.
Multiple symbols for same library unit - Generate multiple variances of a symbol for the same VHDL entity or Verilog module. Create different shape and color symbols for the same library unit.
Route optimization for schematics - Automatically optimize and reduce redundant net segment on schematics.
Annotate Waveform - Place message balloons on waveform for enhanced debugging and documentation.
Support for latest FPGA device - Design flow manager updated to support latest vendor tools and libraries.
New Features and Enhancements: Active-HDL 9.2 Release Notes
What's New Presentation: What's New in Active-HDL 9.2
Riviera-PRO™ 2012.10 available for download November 5, 2012
Riviera-PRO™ 2012.10 delivers numerous stability and performance improvements, new language constructs, and the latest versions of industry-standard verification libraries.
Key changes, updates, and new features include:
New SV constructs ('foreach' and dynamic array size randomization), SVA seq.triggered
Universal Verification Methodology (UVM) library version 1.1c
VHDL 2008 local packages and simulation performance (up to 15% on select designs)
Upgrade to the latest SystemC library version 2.3.0 (IEEE 1666™-2011 Standard)
Improved MATLAB interface (passing structures, and new use scenario / MATLAB as a master)
Enhanced waveform (incremental find, virtual arrays in analog view, simulation messages)
150+ customer requests and issues
ALINT 2012.12™ coming December 2012
ALINT™ design analysis tool decreases verification time dramatically by identifying critical issues early in the design stage.
New Features to look forward to include:
New rules in ALDEC_VLOG and ALDEC_VHDL rule plug-ins to help reduce long routing delays. New rules address issues associated with fanout, logic levels, and output registers.
Tighter integration with Riviera-PRO verification platform. Project teams that develop with Aldec tools will be able to take automated code reviews to the next level by quickly creating project tasks based on violations detected during a linting session. Team members performing code reviews or audits will be able to quickly create and delegate action items to the others.
Instant code analysis in HDL Editor. Instant analysis will be automatically performed while code is being edited. (If new code contains errors, an error marker is displayed on the HDL Editor margin).
HES-DVM™ is a complete ASIC/SoC hardware-based verification solution that provides a unified platform for bit level simulation acceleration, transaction level emulation, system architecture exploration, HW/SW co-verification, virtual modeling and ASIC prototyping.
New Features and updates:
SCE-MI 2.0 Compiler Now Supports:
Easy Hardware Clock Connection for Speed-Bridge with complete integration from within the emulation setup mode. Connects at any hierarchy level and automatically generates implementation constraints for hardware clocks.
4x speed improvement in SystemC co-simulation over previous release. Added static debug probes for support of bits and vectors.
Aldec recently unveiled HES-7™, a scalable, high quality FPGA-based ASIC prototyping solution for SoC/ASIC hardware verification and software validation teams backed by an industry leading 1-Year warranty.
Top Features and Benefits of HES-7 include:
Scalable Capacity Each HES-7 board with dual Xilinx® Virtex®-7 2000T has 4 million FPGA logic cells or up to 24 million ASIC gates of capacity, not including the DSP and memory resources.
Easy To Use with Reduced Design Partitioning Architected to allow for easy implementation and expansion using only one or two large FPGAs, rather than multiple low density FPGAs, HES-7 does not require as much labor-intensive partitioning or tool expense.
Expandable via Non-Proprietary Connector Using a non-proprietary HES-7 backplane connector, HES-7 can easily expand prototype capacity up to 96 million ASIC gates and can include the expansion of daughter boards.
Lowers ASIC Prototyping Cost By keeping costs lower through operational efficiencies, high volume manufacturing, and a close partnership with Xilinx who brings superior design implementation and debug software to the process at affordable prices, Aldec is able to pass savings on to customers.