SOC Central: Verific Design Automation's SystemVerilog, VHDL Parsers Linked with Aldec's Hardware Emulation Solution

Date: Aug 15, 2012Type: In the News

SOC Central: Verific Design Automation's SystemVerilog, VHDL Parsers Linked with Aldec's Hardware Emulation Solution



Printed version of site: www.aldec.com/en/company/news/2012-08-15/130