The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. This year's conference was recently held at the Moscone Center in San Francisco. According to show organizers, show attendance was up 16% over 2011.
Top requests from visitors to Aldec's booth included one-on-one Ask Aldec Q&A Sessions where attendees learned more about the latest product updates, roadmaps and demonstrations. UVM, Hardware emulation solutions, simulation on the cloud and VHDL verification methodology were also popular technical session topics.
Missed DAC? Not to worry, register today to enjoy Aldec's top requested Technical Presentations in a convenient webinar format.
Upcoming Webinar Schedule
Simulation on the Cloud: Unlimited Possibilities
Thursday, June 28, 2012
Aldec has enabled running RTL and Timing simulation on the secured cloud, providing access to a virtually unlimited number of high performance servers. Learn about cloud security, benefits and how to set up and run simulation on the cloud.
OS-VVM: High-Level VHDL Verification
Thursday, July 19, 2012
Standard VHDL has all the features necessary to code randomization of stimulus and functional coverage while verifying larger, system-level designs. Learn how Open Source VHDL Verification Methodology (OS-VVM) makes this easier.
To learn more or register, please visit www.aldec.com/events.
For your convenience, you may also view Aldec’s library of pre-recorded webinars.
EDA’s friendliest robot, Al, was a popular photo op at DAC. Tweet your own photo with Al and mention @AldecInc for a chance to win a $100 Southwest Airlines gift card.