Banbury, United Kingdom – May 9, 2012 Aldec Europe is pleased to report the results of Aldec Inc.’s 2012 verification survey. Conducted annually, this year’s survey examined recent trends in Assertions, Coverage, Testbench Management and Hardware-Assisted Verification; with the primary focus on design verification process automation.
More than 2,400 engineers participated, the highest number since Aldec first ran the survey (in 2008). This year, approximately half of the participants are Design Engineers and a third are Test Engineers. The remaining participants include Software Designers, DSP Developers and Board Designers.
The Aldec survey results revealed that, despite the excitement around SystemVerilog within the industry and the increasing popularity of advanced verification methodologies such as UVM, a significant portion of designers intend to stick with VHDL; for a variety of technical, logistical and financial reasons.
John Aynsley, CTO of industry-renowned training company Doulos, is not surprised by Aldec’s survey results, and comments: “We’re increasingly encountering designers, working in VHDL, that are dealing with bigger and bigger designs. They appreciate the benefits of migrating to SystemVerilog but for some it’s too big a leap to make.”
Despite the common perception that VHDL is a dated language that lacks a number of advanced OOP concepts, it appears VHDL users still perform many of the same tasks as SystemVerilog users. For instance, they are able to: use constrained-random verification techniques, develop in-house verification methodologies, track verification plans, analyse verification trends, rank tests, analyse assertion and coverage reports, and use computing grids.
Aynsley adds: “There is undoubtedly a continued need for VHDL support, particularly in Europe as a geographic region and in some specialist industries such as aerospace. Yes, SystemVerilog is growing in popularity - but in terms of engineers signing up for our training courses worldwide it is only recently that we’ve seen SystemVerilog overtake VHDL. The VHDL language needs to be supported, by vendors and training companies alike, plus initiatives like the recently announced Open-Source VHDL Verification Methodology should be praised for giving the language new momentum.”
Aldec’s survey provides a clear indication that the ‘Next Design Verification Language’ - to be used in isolation or in combination with another language - will not be SystemVerilog. Specifically, respondents were able to select one or more languages for verifying their next project when answering Aldec’s survey question. Of the 2,400+ surveyed, 53% indicated they would be using VHDL (in isolation or in combination with another language). The other languages scored: Verilog (31%), SystemVerilog (32%), SystemC (11%), and C/C++ (23%); noting that the multiple-choice aspect means the total is more than 100%.
With regards to verification, 41% do not follow any particular methodology, 45% employ an in-house developed methodology and the remaining respondents rely on SystemVerilog-based OVM/UVM (17%) and VMM (7%). Again, respondents could make multiple choices, so the total is more than 100%.
Dave Rinehart, Vice President of Aldec Inc., notes: “Aldec is first and foremost a verification company, and because our EDA tools have mixed-language capability we’re of the opinion our annual verification surveys are unbiased. Also, it’s great to see our survey results aligning with what others are seeing in the industry too. VHDL is alive and well.”
Above, the languages to be used in isolation or in combination that the respondents to Aldec’s
survey plan to use to verify their next projects.
Above, a representation of whether or not respondents employ a verification methodology,
and if so which.
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
About the Open Source VHDL Verification Methodology
The Open Source VHDL Verification Methodology (OS-VMM), launched in late 2011, helps engineers tackle challenges presented by their next designs and helps them uncover the hidden capabilities of VHDL 2008. It enables Constrained and Coverage-driven Randomization, as well as Functional Coverage, providing advanced features to engineers while enabling them to continue to develop using VHDL.
For more information please visit www.osvvm.org where users are encouraged to work together to help grow the methodology.
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