Henderson, NV - July 11, 2011 — Aldec, Inc. today announced expanded support for the Universal Verification Methodology (UVM) with comprehensive transaction-level visual debugging. The new capabilities for transactions recording and visualization enable engineers to utilize Riviera-PRO 2011.06 advanced debugging infrastructure without having to manage basic mechanisms for transactions handling.
“Our UVM 1.0 implementation combines the proven debugging capabilities of Riviera-PRO with an industry-standard approach to building reusable and expandable verification environments, providing a more natural way for engineers to comprehend and debug sophisticated verification environments, ” said Dave Rinehart, Vice President, Aldec, Inc.
Riviera-PRO allows analyzing transaction data using the existing Waveform Viewer tool together with the new Transaction Data Viewer that represents transactions as a spreadsheet that offers rich navigation and filtering capabilities. All the debugging tools are well integrated with each other and allow for efficient analysis of transaction-level information, including the cross-probing and viewing of transaction attributes, relations, and linked signals. Based on such a broad range of information about the interactions between testbench and design under test, Riviera-PRO users have extensive visibility into their verification environments.
For additional information, technical papers and presentations detailing Riviera-PRO's Visual Transaction Debugging features, please click here.
The new UVM 1.0 transaction-level debugging capabilities are immediately available with the latest release of Riviera-PRO 2011.06 at no cost to customers with a valid maintenance contract and SystemVerilog verification support.
Riviera-PRO is a complete verification platform that supports the latest versions of industry standard verification libraries such as SystemVerilog UVM 1.0, OVM 2.1.2, and VMM 1.1.1a. In combination with advanced debugging tools, it makes Riviera-PRO an ideal platform for building up layered, coverage driven, constrained-random environments for functional verification of sophisticated ASIC and FPGA designs.
Aldec, Inc., is an industry-leader in Electronic Design Verification and offers a patented technology suite including: Design and Documentation, Design Rule Checking, Functional Simulation and Verification, Hardware-Assisted Verification, IP Cores, DO-254, and Military/Aerospace solutions. For the latest, follow Aldec on Twitter.