Emulation: Thinking outside of the Big Box

Guest Blog by Doug Amos, One-Man-Army FPGA Consultant

Guest Blogger: Doug Amos, One-Man-Army FPGA Consultant
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There’s no question; verification is a massive time drain in SoC and other chip design projects. For many years, those with deep enough pockets have turned to so-called “Big Box” emulators in order to recover some of the time lost on RTL simulation, but what about the rest of us? Is there another way to accelerate verification and reduce our overall project schedule? Yes there is; and at Aldec they call it FPGA-based Emulation.


“FPGAs; aren’t they just for prototyping?”


Sure, FPGAs are the fastest platform for prototyping, but we can also harness that speed into our verification environment, then we can achieve runtime performance 2x to 5x faster than traditional “big box” emulation systems, and all at a fraction of the cost per gate per MHz. The most significant differences between FPGA usage in prototypes and in emulation is shown in table 1.




Speed Limitation

Inter-FPGA signal multiplexing

FPGA-to-Host Comms

Clock Topology


Multiple Clocks

Single System Clock

Inter- FPGA Traces

Flexible, May match
SoC Interconnect

Fixed, Balanced

Stimulus Source

Real-world IO


Signal Capture

Selected Nodes

“Full” Visibility

Memory Modes

Near-match to physical


Table 1: Typical differences between FPGA usage in prototyping and emulation


“FPGAs are way too small for our SoC design, aren’t they?”


In the HES7XV12000 board, Aldec already has the largest capacity single FPGA boards commercially available and in use today. The HES7XV12000 platform (main board shown in figure 1) gives Aldec’s Hardware development team a great starting point for taking FPGA systems to a whole new scale by replacing the six Xilinx XC7V2000T FPGAs with Xilinx’s latest Virtex® UltraScale™-440 devices (see www.aldec.com/ultrascale).

Figure 1: top view of HES-7 main FPGA board


The sheer scale of the latest Xilinx® Virtex® UltraScale™ devices is allowing Aldec to implement over 150 million ASIC gates of SoC design on a single board. These boards can be racked together and then you start to see some really impressive numbers. However, raw FPGA resources don’t make an emulator; power, clocking, memory, connectivity and other hardware resources also need to be provided and in linked efficiently to the simulator running on the host workstation. Years of experience have allowed Aldec to achieve exactly that, but the most critical elements of any emulator are the tools and libraries; making it possible to compile the SoC design into the hardware and then stimulate and debug it when it is there.


“We’re verification guys; we can’t be FPGA experts as well!”


You’re right. In the case of an FPGA-based emulator, we should not be dragged into the low-level details of implementation, such as those commonly associated with FPGA-based prototyping. For emulation, we trade off the maximum possible performance and/or resource utilization for automation and ease-of-use. Our main aim is simulation acceleration, so if automation allows us to accelerate by a factor of 10,000 then few verification teams will tolerate a longer bring-up and iteration time, just in order to stretch that a little to 10,500.


So how do we achieve that automation?


Automation in Aldec’s case is provided by HES-DVM. I should explain that HES stands for Hardware Emulation Solution; a proven technology that is now on its 7th generation; while DVM stands for Design Verification Manager. It is the DVM part that is the major difference between using FPGAs for prototyping and harnessing their massive potential for FPGA-based emulation. It provides all the IP libraries, SCE-MI transactors, compilers, partitioner and mappers required in order to automatically integrate HES-7™ FPGA platforms with the proven Aldec Riviera-PRO™ verification environment and other simulators.


What else can we do with FPGA-based Emulation?


If simulation acceleration isn’t enough of a reason then a summary of some key uses for FPGA-based emulation is shown

in figure 2.


Figure 2: FPGA-based Emulation use modes; thinking outside of the box


For example, how would you like to hook your FPGA-based emulator into an advanced UVM test bench? HES-DVM includes the necessary SCE-MI transactors to allow UVM drivers and monitors to communicate with the DUT in the emulator. If all those acronyms in the previous sentence need some explaining then take a look at Aldec’s website at https://www.aldec.com/solutions/hardware_emulation_solutions/acceleration where you can find more technical detail. SCE-MI transactors also allow the emulator to be driven directly from a SystemC testbench, shown as the right-hand overlap in our emulation Venn diagram.


The third overlap represents the link with virtual platforms. Often the CPU subsystem is included as pre-verified RTL IP, and so many of our cycle-accurate verification tests do not need to extend to the that RTL. However, we will often need to run software on the CPU subsystem in order to verify its integration with the rest of the SoC, this might be as simple as “bare-metal” code or as complex as the full software stack. In many cases, an untimed virtual platform representing the CPU subsystem will be sufficient for these tests, using transaction-level representations such as ARM® Fast Models. SCE-MI transactors also allow us to link our FPGA-based emulator to Fast Models or other transaction-level virtual platforms, opening the door to Hybrid Emulation. Finally, if you are also aiming to create an FPGA-based Prototype of your SoC, then an FPGA-based emulator is a great place to start.


Think you can’t afford emulation? Think again!


Aldec are adopting in their seventh generation Hardware Emulation Solution, HES-7™, heralding a great leap in the capability and economy of FPGA-based emulation. By the way, if you really want it, Aldec can put HES-7 into a box for you, but isn’t the world ready for emulation thinking outside of the box?

Doug has carved out a living from programmable logic and FPGA for over 30 years, holding technical positions with Altera, Synplicity and Synopsys. He did his first programmable logic design in the mid-80’s, and was a freelance consultant designer and “PIP-Pilot” back when LUTs were still a pretty neat idea.

Since then, Doug has designed or supported countless FPGA and ASIC designs either as an independent consultant or working with the leading vendors.

Doug became Synplicity’s first engineer and Technical Director in Europe and has presented widely on FPGA design and FPGA-based prototyping including lead-authoring the FPGA-based prototyping Methodology Manual in 2011.

In all that time, the one constant has been the rapid change within the industry, and despite its maturity, FPGA always offers something new, and that will keep Doug busy for some years to come.

Doug holds a honours degree in Electrical and Electronic engineering from the University of Bath, England.

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  • HW-Assisted Verification


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