Can’t make the webinar? Go ahead and register. You’ll receive a link to view the recording at your convenience. LIVE WEBINAR PRESENTED BY DOULOS ‘Easier UVM: Helping FPGA Designers Get Started with UVM’ Learning and using UVM can seem like a daunting challenge, particularly if you are an FPGA Designer with limited time to dedicate to verification. Nonetheless, UVM does represent best practice in constrained random functional verification, so is something that every digital design and verification engineer should be aware of. In this webinar, we introduce the Easier™ UVM Coding Guidelines and Code Generator from Doulos, and show how Easier UVM can help you start to gain confidence with UVM by generating your own examples that run out-of-the-box. We show examples from the Easier UVM Code Generator running under Aldec Riviera-PRO™. The one hour webinar is broadcast twice at convenient times for international time zones. It is free of charge to attend and is interactive with Q&A participation by attendees throughout. Register for a webinar broadcast that is convenient for you. UK, Europe and Asia: Friday, September 11, 2015 10-11am (BST - UK) | 11am-12pm (CEST) | 2.30-3.30pm (IST) North America: Friday, September 11, 2015 10-11am (PDT) | 1-2pm (EDT) | 6-7pm (BST - UK) Presented by Doulos CTO John Aynsley. Aldec is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. +1.702.990.4400 sales@aldec.com www.aldec.com Don't want to receive email Updates? Unsubscribe here.
