Aldec to offer ‘In case you missed it at DAC’ Tech Sessions Live Online FPGAs for Verification, UVM Simulation Acceleration with Scalable FPGA Platforms Date: Thursday, July 9, 2015 Register for EU 3:00 PM - 4:00 PM CEST Register for US 11:00 AM - 12:00 PM PDT Most ASIC IP and SoC platforms will be validated at some point using FPGAs; this task is typically referred to as ASIC FPGA prototyping. At the same time, FPGAs are increasingly being used for verification due to the performance and scalability of these systems. In this webinar we will introduce an approach where UVM tests can be accelerated with the use of an FPGA co-emulator. The approach is built upon industry standards SystemVerilog and SCE-MI, and requires no changes to the test environment to accelerate. This enables tests to be moved seamlessly from simulation to the accelerator and back again. [Related Article] UVM: What’s Stopping You? More Webinars: Go with the flow (Python) Date: Thursday, July 16, 2015 Register for EU 3:00 PM - 4:00 PM CEST Register for US 11:00 AM - 12:00 PM PDT Eliminating Clock Domain Crossing (CDC) Issues Early in the Design Cycle Date: Thursday, August 13, 2015 Register for EU 3:00 PM - 4:00 PM CEST Register for US 11:00 AM - 12:00 PM PDT Physical Testing for DO-254 Date: Thursday, July 30, 2015 Register for EU 3:00 PM - 4:00 PM CEST Register for US 11:00 AM - 12:00 PM PDT OSVVM for VHDL Testbenches View Recorded Webinar and Slides Aldec Webinar Events can be conveniently attended from your desktop PC or Mac, or from your mobile device. Can’t make the webinar? Go ahead and register, and following the event you’ll receive a link to review a recording. UVM: What’s Stopping You? These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based UVM. Many verification teams have ramped up on UVM, but others have yet to take the plunge. Why is that? And how big a “plunge” is it, anyway? Editorial/In The News SemiWiki: Aldec packs 6 UltraScale parts on HES-7 Aldec HES-7 with Xilinx Virtex UltraScale Devices Enables True FPGA-based Verification [Chip Design] CDC Verification: Using Both Static and Dynamic Checking is Key to Success Aldec is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. +1.702.990.4400 sales@aldec.com www.aldec.com Don't want to receive email Updates? Unsubscribe here.
