Riviera-PRO 2009.10 Trainings

The following training materials are available:
NameDescriptionMain FileAssociated Files
01-Running simulation in the Batch modeLearn how to run simulation in the batch mode .pdf
02-Running simulation in the GUI modeLearn how to run simulation using the GUI operations .pdf
03-Library ManagementLearn how to manage libraries in the batch and GUI mode .pdf
04-TCL Scripting InterfaceLearn how to use TCL commands/scripts with Riviera-PRO .pdf
05-VHDL Performance OptimizationLearn how to improve VHDL simulation performance by adjusting compilation and simulation settings .pdf
06-Verilog Performance OptimizationLearn how to improve Verilog simulation performance by adjusting compilation and simulation settings .pdf
07-Waveform ViewerLearn how to work with waveform viewer and related tools .pdf
08-Advanced DataflowLearn how to use Advanced Dataflow to explore the signals connectivity, traverse the design hierarchy, analyze dataflow, and trace an event backwardly or forwardly to its origin .pdf
09-HDE based debuggingLearn how to debug the source code during the simulation by setting up the breakpoints, stepping through the code, etc. .pdf
10-Debugging ToolsLearn to use various standalone debugging tools to diagnose design problems .pdf
11-X-traceLearn to use X-Trace tool to get information regarding unknown signal values during the simulation .pdf
12-Code CoverageLearn how to use statement, branch, toggle, expression coverage tool to evaluate how efficiently and completely your design was tested .pdf
13-Riviera-PRO 2009.06 Matlab InterfaceLearn how to execute Matlab commands, call M functions and transfer data to and from Matlab workspace from your HDL based design in Riviera-PRO .pdf
14-Riviera-PRO 2009 06 Simulink InterfaceLearn how to generate .m file wrapper for your HDL modules and use them in Simulink so as to be able to run the co-simulation with Riviera-PRO .pdf
15-SystemC SimulationLearn about the seamless interface between SystemC and HDL, and running the simulation, debugging in SystemC – HDL mixed design .pdf
16-AssertionsLearn how to use OVA, PSL and SystemVerilog assertions with various compilation options and debugging tools provided by Riviera-PRO .pdf