| Name | Description | Main File | Associated Files |
| 01-Running simulation in the Batch mode | Learn how to run simulation in the batch mode |
.pdf
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| 02-Running simulation in the GUI mode | Learn how to run simulation using the GUI operations |
.pdf
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| 03-Library Management | Learn how to manage libraries in the batch and GUI mode |
.pdf
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| 04-TCL Scripting Interface | Learn how to use TCL commands/scripts with Riviera-PRO |
.pdf
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| 05-VHDL Performance Optimization | Learn how to improve VHDL simulation performance by adjusting compilation and simulation settings |
.pdf
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| 06-Verilog Performance Optimization | Learn how to improve Verilog simulation performance by adjusting compilation and simulation settings |
.pdf
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| 07-Waveform Viewer | Learn how to work with waveform viewer and related tools |
.pdf
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| 08-Advanced Dataflow | Learn how to use Advanced Dataflow to explore the signals connectivity, traverse the design hierarchy, analyze dataflow, and trace an event backwardly or forwardly to its origin |
.pdf
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| 09-HDE based debugging | Learn how to debug the source code during the simulation by setting up the breakpoints, stepping through the code, etc. |
.pdf
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| 10-Debugging Tools | Learn to use various standalone debugging tools to diagnose design problems |
.pdf
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| 11-X-trace | Learn to use X-Trace tool to get information regarding unknown signal values during the simulation |
.pdf
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| 12-Code Coverage | Learn how to use statement, branch, toggle, expression coverage tool to evaluate how efficiently and completely your design was tested |
.pdf
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| 13-Riviera-PRO 2009.06 Matlab Interface | Learn how to execute Matlab commands, call M functions and transfer data to and from Matlab workspace from your HDL based design in Riviera-PRO |
.pdf
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| 14-Riviera-PRO 2009 06 Simulink Interface | Learn how to generate .m file wrapper for your HDL modules and use them in Simulink so as to be able to run the co-simulation with Riviera-PRO |
.pdf
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| 15-SystemC Simulation | Learn about the seamless interface between SystemC and HDL, and running the simulation, debugging in SystemC – HDL mixed design |
.pdf
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| 16-Assertions | Learn how to use OVA, PSL and SystemVerilog assertions with various compilation options and debugging tools provided by Riviera-PRO |
.pdf
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