DO-254 CTS
The Aldec
DO-254 CTS (Compliance Tool Set) provides support for the “Design Assurance Guidance for Airborne Electronic Hardware” (DO-254/ED-80) chapter 6.2 "Verification Process" and chapter 11.4 “Tool Assessment and Qualification Process”. Aldec provides a fast and reliable verification process for assurance levels A, B, C and D with a focus on increased testability in hardware together with the design requirements traceability.
Top Features
- Design verification in the target device
- In-Hardware verification performed at speed
- Same number of tests run in the target device as in the simulator with 100% test coverage assured
- Automated output waveform comparisons between the HDL simulation and in-hardware testing results
- Technology Patent no. 5,479,355; System and method for a closed loop operation of schematic designs with electrical hardware
- DO254 Compliance Verfication Process Overview
Aldec's HDL Simulation Tool Suite provides HDL simulation (source level), post-synthesys (gate level) and post place-and-route simulation (timing level), all performed in one software environment. The tool Suite combines code linting, code coverage, profiling, automated documentation and waveform comparison tools to enhance verification productivity. The simulator uses the designer-created testbench to verify the design functionality and provides coverage metrics to measure how effectively the testbench has exercised the design. The simulation results are stored in the waveform format and automatically compared to the results from the different stages of simulation.