Riviera-PRO 2009.06 Configurations (Feature Matrix)

Riviera-PRO 2009.06
Features
x
(LV)
x
(LVT)
x
(LVT-SV)
Supported Languages
EDIF 2 0 0
VHDL IEEE 1076 (1987, 1993, 2002 and 2008)
Verilog® HDL IEEE 1364 (1995, 2001 and 2005)
SystemVerilog IEEE 1800 (Design)
SystemVerilog IEEE 1800 DPI 2.0
SystemC™ 2.2 IEEE 1666/OSCI 2.2/TLM 2.0  
PSL IEEE 1850  
SystemVerilog IEEE 1800 Assertions  
SystemVerilog IEEE 1800 (Verification) - Partial Support    
Design Entry and Design Management
HDL and Text Editor
Syntax highlighting and Auto-Complete (HDL, PSL and SVA)
Design Manager
Macro, Tcl/TK, Perl script support
HDL Debug and Analysis
Interactive Code Execution Tracing
Advanced Breakpoint Management
Accelerated Waveform (ASDB)
Hierarchical References to/from VHDL (Signal Agent)
Post Simulation Debug
Waveform Compare
Memory Viewer  
Integrated Source Level C/SystemC Debugger  
Synopsys SmartModels®, SWIFT™ Interface and LMTV  
SpringSoft® Verdi™ PSD mode Interface  
X-Trace  
Advanced Dataflow  
Simulation/Verification
Single or Mixed Language
Verilog Programming Language Interfaces (PLI/VPI)
VHDL Programming Language Interface (VHPI)
Value Change Dump (VCD and Extended VCD) Support
Platform Independent Libraries
Simulation Model Protection/Library Encryption
Library Refresh
VHDL/Verilog Synplicity Compatible Encryption
Verilog HDL Simulation Optimization
VHDL Simulation Optimization
Profiler (Performance Metrics)  
SFM (Server Farm Manager)    
Coverage Tools Bundle
Statement, Branch, Expression and Condition Coverage  
Toggle Coverage  
Co-simulation and C-Synthesis
Simulink® Co-simulation  
MATLAB® Co-simulation  
Assertions Bundle
SVA, PSL, OVA Assertions and Cover  
Assertions & Cover Viewer, Waveform Viewer, Debugging Tools  
Design Rule Checking
ALINT™ with Basic Rule Library Option
STARC® VHDL Rule Library Option Option Option
STARC® Verilog Rule Library Option Option Option
Licensing
Floating License
Supported Platforms
Windows® 2000/2003/XP/Vista
Linux x86/x86_64