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Configurations
Riviera-PRO 2008.06 Configurations (Feature Matrix)
Riviera-PRO 2008.06
Features
x
(LV)
x
(LVT)
x
(LVT-SV)
Design Management
Design Manager
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Design Entry
Language assistant with templates and auto-complete
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Macro, Tcl/TK, Perl script support
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HDL and Text Editor
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Simulation/Verification
VHDL IEEE 1076 (1987, 1993, 2002 and 200x)
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Verilog® HDL IEEE 1364 (1995, 2001 and 2005)
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SystemC™ 2.2 IEEE 1666/OSCI 2.2
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SystemVerilog IEEE 1800 (Design)
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SystemVerilog IEEE 1800 (Verification)
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SystemVerilog IEEE 1800 Assertions and Coverage
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PSL IEEE 1850 Assertions and Coverage
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OpenVera Assertions and Coverage
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EDIF 2 0 0
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VHDL Programming Language Interface (VHPI)
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Verilog Programming Language Interface (PLI/VPI)
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Verilog-RTL Gate & Timing Simulation Acceleration
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VHDL RTL and Vital Optimization
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Single or Mixed Language
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Platform Independent Libraries
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Library Management
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Library Refresh
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Simulation Model Protection/Library Encryption
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VHDL/Verilog Synplicity Compatible Encryption
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64-bit Simulation
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Value Change Dump (VCD and Extended VCD) Support
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SFM (Server Farm Manager)
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Debug
Interactive Code Execution Tracing
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Advanced Breakpoint Management
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Accelerated Waveform and List Viewer (ASDB)
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Waveform Compare
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Memory Viewer
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Advanced Dataflow
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X-Trace
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Profiler (Performance Metrics)
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Signal Agent (VHDL and Mixed Only)
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Basic Lint (Verilog and VHDL)
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Extra Standalone Accelerated Waveform Viewer (ASDB)
Option
Option
Option
Advanced Lint – STARC (Verilog Only)
Option
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Integrated Source Level C/SystemC Debugger
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External Simulation Interfaces
Synopsys SmartModels®, SWIFT™ Interface and LMTV
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Novas FSDB Writer
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Denali Memory Model Interface (Verilog and VHDL)
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Coverage Tools
Statement and Branch Coverage
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Toggle Coverage
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Expression Coverage
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Co-simulation and C-Synthesis
Simulink® Co-simulation
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MATLAB® Co-simulation
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Licensing
Floating License
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