Riviera-PRO 2008.06 Configurations (Feature Matrix)

Riviera-PRO 2008.06
Features
x
(LV)
x
(LVT)
x
(LVT-SV)
Design Management
Design Manager
Design Entry
Language assistant with templates and auto-complete
Macro, Tcl/TK, Perl script support
HDL and Text Editor
Simulation/Verification
VHDL IEEE 1076 (1987, 1993, 2002 and 200x)
Verilog® HDL IEEE 1364 (1995, 2001 and 2005)
SystemC™ 2.2 IEEE 1666/OSCI 2.2  
SystemVerilog IEEE 1800 (Design)
SystemVerilog IEEE 1800 (Verification)    
SystemVerilog IEEE 1800 Assertions and Coverage  
PSL IEEE 1850 Assertions and Coverage  
OpenVera Assertions and Coverage  
EDIF 2 0 0
VHDL Programming Language Interface (VHPI)
Verilog Programming Language Interface (PLI/VPI)
Verilog-RTL Gate & Timing Simulation Acceleration  
VHDL RTL and Vital Optimization  
Single or Mixed Language
Platform Independent Libraries
Library Management
Library Refresh
Simulation Model Protection/Library Encryption
VHDL/Verilog Synplicity Compatible Encryption
64-bit Simulation  
Value Change Dump (VCD and Extended VCD) Support
SFM (Server Farm Manager)    
Debug
Interactive Code Execution Tracing
Advanced Breakpoint Management
Accelerated Waveform and List Viewer (ASDB)
Waveform Compare
Memory Viewer  
Advanced Dataflow  
X-Trace  
Profiler (Performance Metrics)  
Signal Agent (VHDL and Mixed Only)  
Basic Lint (Verilog and VHDL)  
Extra Standalone Accelerated Waveform Viewer (ASDB) Option Option Option
Advanced Lint – STARC (Verilog Only)   Option
Integrated Source Level C/SystemC Debugger  
External Simulation Interfaces
Synopsys SmartModels®, SWIFT™ Interface and LMTV  
Novas FSDB Writer  
Denali Memory Model Interface (Verilog and VHDL)  
Coverage Tools
Statement and Branch Coverage  
Toggle Coverage  
Expression Coverage  
Co-simulation and C-Synthesis
Simulink® Co-simulation  
MATLAB® Co-simulation  
Licensing
Floating License