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Configurations
HES 2009.12 Configurations (Feature Matrix)
Display Movies
HES 2009.12
Features
Movies
x
Prototyping (Proto)
x
Acceleration (Xcell)
x
HW/SW Co-Verification (Co-Verify)
x
Emulation (Elite)
Hardware Emulation System
Design Verification Manger [DVM™]
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Daughterboard Connection (connection to external boards and/or devices)
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Super Macro support (groups modules together for increased performance)
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Manual Design Partitioning (manual mapping based on resource information)
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Automatic Design Partitioning – with signal multiplexing using LVDS
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Blackbox Functionality (excludes modules from acceleration)
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Testbench Optimizer – VHDL to C++ Conversion
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Device Debugging (debug of internal hardware signals in simulator)
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Clock Conversion and Analysis (convert multiple clock domains to one)
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Memory Model Mapping (maps user memory to on-board memory)
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Prototyping API and function library (interface with C++ domain)
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Interface to Xilinx ChipScope™ Pro (device debugging)
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Emulation Mode (design clock up to 10MHz)
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Emulation Results Stored in Waveform (ASDB and VCD)
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Emulation Debugging
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Multi-Chip Design Access (ability to use multi-chip FPGA boards)
Option
Option
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Interface to Hardware Boards – includes drivers (Aldec, HAPS or DINI)
Option
Option
Option
Option
HDL Simulator Interface (Aldec, Cadence, Mentor or Synopsys)
Option
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Option
Debugging in SCE-MI Co-emulation
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Dynamic Debugging over Xilinx Readback
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OVL Assertions Support
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Linux, Windows® 2000/XP/Vista
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Prototype Simulation with C/C++ Testbench
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SCE-MI 2.0 Interface Support Emulated Design
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