Active-HDL 8.2 Movies

Title Description Updated
Advanced Dataflow
Advanced Dataflow See how the Advanced Dataflow window displays interconnections of an active design. Concurrent statements, port maps, signals, nets, and registers from all units on all hierarchy levels are flattened and displayed as a single-level diagram. 7/28/2009
Code2Graphics™ Converter
Code 2 FSM Allows conversion of HDL code or EDIF netlist into a Finite State Machine 7/28/2009
Code 2 Graphics Allows conversion of HDL code or EDIF netlist into a Block Diagram 7/28/2009
Design Flow Manager for All FPGA Vendors
Altera Quartus Flow Seamless integration with Altera Quartus tools using Design Flow Manager; Post-synthesis files, library and netlist automatically attached to Active-HDL project 7/28/2009
Fpga Synthesis and Implementation Seamless integration with Xilinx tools using Design Flow Manager; Post-synthesis files, library and netlist automatically attached to Active-HDL project 7/28/2009
Using Active-HDL with Synplify Seamless integration with Synplify tools using Design Flow Manager; Post-synthesis files, library and netlist automatically attached to Active-HDL project 7/28/2009
Design Manager
Creating Design with Sources Create a new desgin using existing VHDL and Verilog source files. Use both files from the local folder and links to files located elsewhere. 7/28/2009
Export to PDF/HTML/Bitmap Graphics
Design Documentation Provides various export options - HTML, PDF and graphics appropriate for MS® Word 7/28/2009
HDL, Text, Block Diagram and State Machine Editor
Block Diagram Editor Graphical entry tool for VHDL, Verilog and EDIF designs 7/28/2009
Creating State Diagrams Quick and convenient creation of diagrams for Finite State Machines, and HDL code generated automatically from the diagram 7/28/2009
HDL Creation Wizards and Language Assistant, column selection, commenting and uncommenting blocks of text 7/28/2009
HDL Features PART 2 Wizards and Language Assistant, column selection, commenting and uncommenting blocks of text 7/28/2009
IP Core Component Generator
IP Core Generator Rich set of parameterized, synthesizable HDL modules, including behavioral code 7/28/2009
MATLAB® Co-simulation
Interface to MATLAB Interface to MATLAB 10/7/2009
MATLAB Verilog Extend the computing power of Verilog with MATLAB® formulae or through execution of m-files. Visualize data with MATLAB® graphical tools 7/28/2009
MATLAB VHDL Extend the computing power of VHDL with MATLAB® formulae or through execution of m-files. Visualize data with MATLAB® graphical tools 7/28/2009
Memory Viewer
Memory Viewer Debugging features - displays memory objects in the current design, modify values in the memory cells 7/28/2009
Post Simulation Debug
Debugging Source code debugging, Setting breakpoints, Watch Window, Waveform Viewer, List Viewer 7/28/2009
Pre-compiled FPGA Vendor Libraries
Library Manager - Precompiled Libraries Manage libraries in Active-HDL. Browse, create, attach, detach, and compact libraries. Change library mode from read-only to read-write and make libraries global. Copy declarations and instantiations of units visible in the Library Manager. 7/28/2009
Profiler (Performance Metrics)
Design Profiler Track CPU activity during simulation; identify sections of code that strain simulation 7/28/2009
Revision Control Interface
Revision Control CVS Use revision control to monitor history of changes in source files and other design resources. Set up CVS as the source control provider. Add files to CVS, check files out, and commit files to CVS. 7/28/2009
Running Active-HDL from 3rd party tools
Starting Active-HDL as the Default Simulator in Actel Libero See how to start Active-HDL simulator right from Actel Libero to run "pre-synthesis", "post-synthesis" and "post-layout" simulations. 7/28/2009
Starting Active-HDL as the Default Simulator in Altera Quartus II See how to run Active-HDL simulator directly from Altera® Quartus software using Native Link feature. 7/28/2009
Starting Active-HDL as the default simulator in Xilinx ISE See how to start Active-HDL simulator from Xilinx ISE Project Navigator to run behavioral and timing simulations. 7/28/2009
Simulink® Co-simulation
Simulink Simulink Interface 7/28/2009
Statement and Branch Coverage
Collecting Code Coverage Statistics collecting code coverage statistics, analyzing the data (No audio) 7/28/2009
Support for Multi-Design Workspace
Workspaces Organize your designs into a workspace. Save time by automating workspace compilation. Archive workspaces. 7/28/2009
SystemC™ 2.2 IEEE 1666/OSCI 2.2/TLM 2.0
SystemC Simulation Creation and compilation of SystemC files, library handling, and simulation in Active-HDL 7/28/2009
Testbench Generation from State Diagram
FSM Testbench Automatic testbench generation from state machines, and the possible strategies involved 7/28/2009
Testbench Generation from Waveforms
Testbench Generation Automatic simulation testbench generation from test vector files 7/28/2009
Timing Simulation Simulate netlists generated by vendor implementation tools. Load timing data from an SDF file 7/28/2009
Toggle Coverage
Toggle Coverage Locate signals that were not assigned any value during simulation (helps to verify if more testing is required) 7/28/2009
Waveform Comparision
Waveform Comparison Compare waveforms, report their differences, and share in HTML 7/28/2009
Waveform Editing waveform editing 7/28/2009
Waveform Viewer (AWF and ASDB)
Waveform - Advanced Zooming and formating, port and signal manipulations, cursor and measurements, bookmarks, comments and browsing 7/28/2009
Waveform - Basic standard waveform viewer, Powerful waveform editing capabilities 7/28/2009
X-Trace
X-Trace Detect X values during simulation. Stop simulation when an X occurs and locate the source of an X value with the Advanced Dataflow window. 7/28/2009