Acceleration - Emulation
HES™ is a versatile emulation and acceleration solution for large complex ASIC and SOC designs which require millions of simulation cycles. The strength of the tool is in automatic design compilation, standard testing interface, integration with industry leading hardware/software debugging tools and the power to transform your existing ASIC prototyping into dynamic emulation.
Top Features
- SOC (ASIC and FPGA)
- Functional RTL acceleration
- Emulation at 10MHz (TLM)
- Transaction Level Interface (SCE-MI 2.0, SystemC C/C++)
- Ultra-Fast DebuggerTM
- DINI and HAPS hardware support