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Play Webinar

Title: SystemVerilog: Who? What? When? Where?

Description: Abstract: SystemVerilog was released as a complete standard in 2009 and will stay with the digital design community whether we like it or not. Quite surprisingly, the only group of people that welcomed SV enthusiastically was the Verification Engineer Guild. Other groups still seem to treat SV with reserve, partially justified by unbearably wide scope of the new language. This presentation explains which areas of SystemVerilog should be implemented by hardware designers. Main topics include Design Subset, Assertions, Verification Subset, Verification Methodologies (OVM/UVM).


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