White Papers

Abstract: The first decade of the 21st century brought tremendous growth of the size of typical digital design, triggering growing demands for faster, safer and more thorough verification. In response to those demands, many new flavors of verification were invented and implemented in the tools, making engineers face difficult choices. This paper gives detailed overview of currently available verification methodologies suitable for large designs and shows how Aldec tools can help in their implementation.

DO-254 is officially enforced by the FAA and other worldwide certification authorities as a means of compliance for the development of airborne electronic hardware incorporating devices such as FPGAs, PLDs and ASICs. DO-254 is rapidly becoming the de-facto standard to all safety critical applications not only in avionics but also in medical, automotive and nuclear industries. Despite of its wide applications, DO-254 is still poorly understood and implementing it remains unclear.

Abstract: Modern digital designs reach the scale of complete systems and require support of Constrained Random Test and Functional Coverage in verification. Although VHDL does not have built-in, direct support for those methodologies, there are neat solutions that allow their quick implementation in your testbench.

Abstract: Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform.

Abstract: This White Paper points out the most significant issues which can be encountered during DO-254 compliant verification process of FPGA designs. It proposes the methods of saving development time during the functional verification process by reusing the work done during RTL simulation for in-hardware at-speed testing in target FPGA devices, which assures a high visibility of results and good traceability of requirements.

Abstract: Growing customer requirements and technological abilities increase the design complexity of hardware and software. Time to market is shortening as well as the lifetime of new designs. In order to be able to meet all those requirements a new approach to the design process is required.

Abstract: The Aldec DO-254 Compliance Tool Set (CTS) provides support for the “Design Assurance Guidance for Airborne Electronic Hardware” (DO-254/ED80) Chapter 11.4 “Tool Assessment and Qualification Process”. Aldec provides support for assessment and qualification of the design and verification tools used in the design of complex electronic hardware such as FPGA, PLD and ASIC devices.

Abstract: Typical ASIC front-end and back-end implementation process involves HDL simulation as a method of verifying design netlist functionality at each stage of the flow. Although HDL simulation is considered accurate it suffers from very low execution speed.Aldec provides the DVM software that allows reusing your existing FPGA prototyping board as a platform for hardware acceleration of HDL simulation.

Abstract: Size of new designs has grown so much that it easily allows creation of the entire system containing microprocessor unit and peripherals on one chip. Verification of such designs can no longer rely on software only, since simulation of MPU does not allow fast enough testing of application software and formal tools handle system hardware only. The use of FPGA-based prototyping boards creates fast and economical solution to this problem. This paper presents one practical implementation of Prototyping Board Verification and Integration Platform.

The most commonly used approach to analyzing objects in an HDL design, is based on the well-known digital waveforms available with any commercial simulator today. Such a time domain representation of data with respect to time, allows verifying many parameters of a designed digital system, but it may not be efficient for applications such as image processing, digital filter design, embedded system design, and others. This document presents Plot, a new solution for a graph-based analysis of HDL objects, correlations between them, and a number of practical applications for it.

Digital circuit designer very frequently faces the dilemma: how to implement arithmetic operations in his or her design. This article presets balanced solutions that provides high level of functionality and maintains decent readability of the code.

Abstract: This white paper presents how to use modern verification techniques for advanced ASIC and SoC designs. Network based application has been selected for this study as a real life design project. Verification process will be performed using Aldec hardware emulation system called HES with transaction based SCE-MI interface used for testing activities. The key objective is to perform the verification of the Ethernet Network Switch with real data delivered directly from Ethernet network in very limited time assigned for verification setup process.

Abstract: Virtual platforms play a significant role in system level development, but they require the speed that emulation systems provide for hardware/software co-verification. This white paper describes a high performance virtual modeling solution achieved by integrating Aldec’s Transaction Level Emulation System with Imperas’ OVP™ (Open Virtual Platforms) and OVPsim™ (OVP simulator). Hardware and Software design teams are now able to simulate and debug virtual models of processors, memories and peripherals while the rest of the system resides in the emulator board running at MHz clock speeds.