Seamless integration of Active-HDL™ and Riviera-PRO™ with MathWorks™ MATLAB®/Simulink® and Agilent™ SystemVue® tool suites provides an efficient cross-domain solution for co-design and co-verification of system-level designs with HDL based implementations.
As a part of the integration flow, Aldec enables hardware-in-the-loop (HIL) capability by linking the model-based design environments with FPGA board. Customers can either leverage Aldec’s off-the-shelf HES-DVM™ and HES-7™ products or any custom in-house board with PCIe interface.
Native support for IEEE 754-2008™ floating-point arithmetic throughout the entire Riviera-PRO™ development environment, and the Plot window, a unique tool for visualization and analysis of large data sets, enable you to focus on your DSP design rather than testbench automation techniques.
Aldec works in close collaboration with all the major silicon vendors, including Altera, Xilinx, Microsemi, and Lattice, to ensure that you get well-integrated and efficient FPGA DSP design and verification flow; Aldec simulators are tightly integrated with your target vendor tools, enabling you to build an advanced verification environment and run RTL, post-synthesis, and post-implementation simulations for designs that use target vendor’s simulation libraries and IP.
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