The Mirror-Box debugging technology used for acceleration allows any component of the accelerated design at any hierarchical level to be mirrored such that two implementations of the same component can be selected for simulation. One implementation is the original RTL code and the other is its FPGA counterpart.
- Generates two implementations of instance selected as Mirror-Box
- Mirrored instance resides in FPGA hardware
- Mirror Box resides in HDL simulator
- DUT resides in FPGA hardware
- Mirror Box output checker in simulator provides run-time outputs comparison
- Additional multiplexer in FPGA allows switching active driver between Simulator and FPGA implementations
- Doubles debugging productivity and turnarounds. Faster detection of bugs per day!
- Switch easily between HDL and FPGA without rerunning Synthesis and P&R
- Quick modification of the HDL code for debugging while rest of DUT resides in the FPGA
- Minimize number of FPGA rebuilds
- Quick smoke-tests run with Mirror-Box code changes in HDL
- Rebuild FPGA only for complete regressions
- Discover hardware implementation defects in simulation environment
- Automatic generation of assertion code to compare FPGA and simulation model