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HVD Technology

Aldec HVD (Hardware-based Visibility Debugging) technology analyzes design RTL sources to identify minimum set of debugging probes that must be present in the emulation hardware to guarantee 100% debugging visibility. During hardware emulation runtime HVD based data extender calculates any design probes that have not been captured directly from the emulator to provide full visibility. For a typical SoC (System on Chip) design it allows to cut down amount of data that needs to be preserved and captured from emulator down to 30% (up to 70% savings). DVM software with HVD Analyzer is used to setup the design for SCE-MI (Standard Co-Emulation Modeling Interface) based emulation and debugging. It assures full build automation including design partitioning and clocks mapping to FPGA prototyping board.
 

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KEY Benefits

  • Improves speed and visibility for hardware debugging
  • Minimizes number of signals for dumping during emulation
  • Provides 100% visibility for dynamic debugging
  • Integrates with Riviera-PRO framework for debugging visualization and true RTL traceability