Emulation is a verification mode in which the entire DUT and synthesizable portions of the testbench are partitioned and implemented in the FPGA board to obtain MHz emulation speed and simulator-like debugging capabilities. There is no constant connection with the workstation or HDL simulator so that the emulated design can run at MHz speed. Emulation can be used for SoC/ASIC system architecture exploration, system validation, HW/SW co-verification or virtual modeling.


The design emulation can be driven by the main two types of data:

  • C++/SystemC transaction level testbenches through the transaction interface standardized as SCE-MI by Accellera
  • Real data: Video, Communication protocols, AHB protocols via Speed-Bridges

HES/DVM DVM ELITE provides a transaction-based verification environment in which the communication interface is based on the SCE-MI standard from Accellera. SCE-MI provides free communication interface suitable for high performance transactional emulators. This standardized interface ensures portability of the verification environment for other emulation platforms. HES/DVM ELITE provides SCE-MI API, synthesizable models of support macros for transactors and other components of SCE-MI infrastructure.


Debugging Capabilities

  • Dynamic Debugging - provides 100% design visibility and full integration with Riviera-PRO simulator
  • Static Debugging - provides very fast access to a number of pre-configured debugging probes
  • Emulation triggering and control capabilities
  • Memory visibility & write access tools
  • Availability of high density (large pin count) connectors to hook other hardware including embedded processor debuggers


Key Benefits

  • HW/SW Co-Verification, Transaction Level Modeling
  • Co-verification of the entire SoC with MHz emulation speed
  • OS bootup and firmware execution on the verification platform
  • Source level software debugging
  • Hardware debugging using static and dynamic probes (100% visibility)