UVM Transaction Debugging
|Press Release||Aldec Adds UVM Transaction-Level Visual Debugging|
|Presentation||UVM Transaction Debugging|
|Solutions||UVM, OVM and VMM|
|Webinar||Introducing Transactions in Design Verification|
Much like metadata coded in the design, transactions provide a more natural way for engineers to comprehend and debug sophisticated verification environments by giving a high-level view into the behavior of the design. By checking transaction streams, you can quickly see that an endpoint device is sending a frame, a CPU is servicing an interrupt, etc. With such a visual information readily available, you do not have to analyze events on multiple signals to find out what the design is doing. The ability to define relations between transactions or link signals to transaction streams also provides even more power in visualizing the relationships between the design objects and events.
Riviera-PRO provides the Transaction Level Modeling (TLM) interfaces for use with VHDL, Verilog/SystemVerilog, and SystemC industry standard languages. The TLM interfaces have been also implemented in the SystemVerilog UVM/OVM and SystemC Verification (SCV) libraries delivered with Riviera-PRO. By using these interfaces, transaction-level data is recorded to an Aldec Simulation Database (ASDB) to allow utilization of Riviera-PRO's advanced debugging infrastructure instead of the default text-based mechanisms for transactions handling.
Riviera-PRO allows analyzing the transactions using the Waveform Viewer and Transaction Data Viewer that represents transactions as a spreadsheet full of rich navigation and filtering capabilities. All debugging tools are well integrated with each other and allow for efficient cross-probing and viewing transaction attributes, relations, and linked signals.