OS-VVM™

The well-recognized languages of VHDL and Verilog provide the ability to create complex FPGA and ASIC designs, however designers must then turn to hardware verification languages such as SystemVerilog or SystemC to bring random values generation to the tests or to collect functional coverage automatically.

Open Source VHDL Verification Methodology (OS-VVM) includes VHDL based verification packages that enable:

1. Generation of random values for signals and variables of various types. The generation can be constrained with the range and weight for random numbers.

2. Definition of the functional coverage model with the simple cover points, cross points, and intelligent coverage to achieve functional coverage faster. The coverage goal can be specified for each point, i.e. the number of times a point must be hit to be considered as covered.

OS-VVM is the most efficient when used with Transaction Level Modeling (TLM) which is demonstrated in the included FIFO example. The usage model in the examples has been specifically kept light and simple with an easy to follow test structure to minimize the learning curve and facilitate methodology adoption.

The OS-VVM has been produced as a joint effort between Aldec and SynthWorks, both companies committed to provide continued support to VHDL design community. The source code of the library has been developed using IEEE 1076-2008 VHDL enabling it to run on a single language VHDL license.