Phase-Based Linting (PBL)
The Phase-Based Linting (PBL) methodology puts clear priorities into the design analysis process by reducing the total number of issues to be addressed and minimizing the number of design refinement iterations. It speeds up debugging time by 3—10X compared to the traditional approach.
Summary on the key features:
Design Rule Checker
ALINT™, Aldec's advanced Design Rule Checking Tool helps detect a wide variety of design problems, including poor coding styles, improper clock and reset management, simulation, synthesis problems, poor testability and source code issues throughout the design flow.
ALINT provides extensive checking of the quality of VHDL and Verilog® code using a set of design rules established by STARC® (The Semiconductor Technology Academic Research Center) from Japan as well as rules developed by Aldec(ALDEC, DO-254, and RMM rule plug-ins).
ALINT features a unique framework that combines all necessary tools for easy set up of the design checks, linting and results analysis and debugging. Creation of custom rules is supported.