Active-HDL EDU Configurations

The ability to quickly document designed components is becoming critical with the increased complexity of designs, ubiquitous IP re-use, and design teams scattered across many floors, departments, or countries. More   

With Active-HDL, you can mix different types of descriptions. Your design can include textual HDL code as well as block diagrams and state diagrams. More   

Code2Graphics More   

The IP CORE Generator is a tool built-into Active-HDL that comes with a rich set of parameterized modules. They are ready-to-use in any VHDL- or Verilog-based system. More   

Powerful testbench generation automation features have been provided to speed functional verification. A testbench for any design unit can be generated from waveforms created in the waveform editor or during a simulation run. More   

The Design Flow Manager configures, constrains and executes simulation, synthesis and implementation tools for all devices from Altera®, Atmel®, Lattice®, Microsemi™ (Actel), Quicklogic®, Xilinx® and more in one integrated development environment. More   

Designers can open multiple Active-HDL designs simultaneously and integrate them into one super-project. More   

ALDEC simulators provide full support of the IEEE 1076-1993 Standard, IEEE 1076™-2002 VHDL standard and majority of just published IEEE 1076™-2008 Standard. More   

ALDEC simulators provide full support of the IEEE 1364-2005 Standard. To enable simulation of a large variety of Verilog designs, both legacy and new, ALDEC simulators can be set to work in Verilog ’95, 2001 and 2005 modes. More   

SystemC is an environment that allows description and verification of digital systems using C++. More   

SystemVerilog is a set of extensions to the Verilog HDL that allow higher level of modeling and efficient verification of large digital systems. More   

Simulation of netlist in EDIF 2 0 0 format is supported by most Aldec Simulators. More   

The Verilog PLI (Programming Language Interface) and VPI (Verilog Procedural Interface) provide a standard mechanism to access and modify data in a simulated Verilog model. More   

Accelerated Waveform Viewer More   

Language Assistant with Templates and Auto-complete More   

Aldec simulators integrate The MathWorks' intuitive MATLAB language and a technical computing environment. More   

Node Locked License More   

One Year Time Based License (TBL) grants a designer a license to use the product for a period of one year. A 1 year support contract is included with the purchase of TBL license. More   

Builds are tested on all the latest platforms, including Windows 7, to ensure correct operation on users' workstations. More