Events Schedule

The FPGA Forum is the annual meeting place for FPGA environment in Norway, where FPGA designers, project managers, technical leaders, scientists, last year students and major suppliers gather for a 2-day practical focus on FPGA. FPGA forum offers in addition to an excellent opportunity to meet and exchange experience in the FPGA environment in Norway - both during breaks and during the social event of the evening.

Aldec, Inc. in partership with local distributor, FirstEDA  will present the following tracks:

Advanced FPGA Verification: VHDL -2008 and Static Design Rule Checks
VHDL is still the most important hardware description language for FPGAs and ASICs in Europe. ALDEC will continue to support new VHDL standards with a high priority and is currently the leading supplier of VHDL 2008 simulators. VHDL 2008 offers some language enhancements for a more powerful and easier to use VHDL. Simulation is good for checking the functionality of the design against the expectations of the developer. Since VHDL is still intended to be a modeling language some constructs could cause functional differences between the RTL model and the synthesized gate level implementation. Static design rule checks are helping to recognize those issues in advance.

Assertions: A Practical Introduction for HDL Designers
The majority of FPGA designers who are proficient in traditional HDLs might have heard about assertions, but haven’t had time to try them out. Designers should be aware that assertions are quickly becoming standard part of both design and verification process, so learning how to use them is a future necessity. This presentation provides a quick and easy introduction to the basic ideas and applications of assertions: sequences, properties, assert and cover commands, etc., as well as practical examples.

EWCI is organized by the India Chapter of Association of Old Crows (AOC), Bangalore in collaboration with The Shephard, UK and supported by Defense Research and Development Establishment (DRDO), India. The Conference addresses the technical and commercial needs of Operational Users, Planners, Developers, Procurers, Testers and Trainers of the latest EW Technologies and Systems. This year’s theme, “EW: Collaborate and Achieve” represents EWCI’s rofessionals who would collaborate for the future developments in the field at global level.

DVCon is the premier conference for functional design and verification, focused on bringing information from the leading edge of technology, techniques, standards and methods.

The European event for Electronic System Design and Test.
http://www.date-conference.com/

The Spacecraft Technology Expo brings together global decision makers, OEMs, supply chain experts, industry executives, suppliers and customers to identify present and future market growth opportunities for the design, manufacture, pre-launch testing and operations of spacecraft, satellites, and space-related technologies. A comprehensive three-day technical conference program will be built around the needs and priorities of key industry technology leaders in spacecraft and satellite design, build, and testing.

The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. Now in its 49th year, DAC features a wide array of technical presentations, as well as more than 200 of the leading electronics design suppliers in a colorful, well-attended trade show that, literally, attracts stakeholders from around the world.

Date: Thursday, Feb 16, 2012
Time: 11:00 AM - 12:00 PM PST

When it comes to debugging during emulation, engineers are forced to use multiple applications to ensure proper hardware signal data extraction and visualization.  Learn from this webinar a leading edge technology that intelligently extracts data from the FPGA emulator to provide 100% signal visibility during emulation.  This approach delivers up to 70% bandwidth savings in the critical emulator communication channel.  Both dynamic and static probes from emulation can also be visualized in the Riviera-PRO waveform viewer preserving the original signal names and hierarchy paths and providing complete traceability to the design’s RTL source code.

Agenda:

• Introduction
• Emulation Debugging Concepts
• 100% Visibility during Dynamic Debugging
• Live Demonstration
• Q & A

Date: Thursday, Feb 16, 2012
Time: 3:00 PM - 4:00 PM CET

When it comes to debugging during emulation, engineers are forced to use multiple applications to ensure proper hardware signal data extraction and visualization.  Learn from this webinar a leading edge technology that intelligently extracts data from the FPGA emulator to provide 100% signal visibility during emulation.  This approach delivers up to 70% bandwidth savings in the critical emulator communication channel.  Both dynamic and static probes from emulation can also be visualized in the Riviera-PRO waveform viewer preserving the original signal names and hierarchy paths and providing complete traceability to the design’s RTL source code.

Agenda:

• Introduction
• Emulation Debugging Concepts
• 100% Visibility during Dynamic Debugging
• Live Demonstration
• Q & A

Date:Thursday, Mar 8, 2012
Time: 3:00 PM - 4:00 PM CET

Creating and verifying a mixed-signal IC design (a chip containing both analog and digital parts) is a challenge. SPICE based simulation provides the accuracy needed by the analog design but is too slow to deal with digital part. Event-driven digital simulation can handle digital portion, but fails when dealing with the analog design. The best method of solving this verification problem is to create a smart interface between the SPICE engine and the high-performance digital simulator.

Attend our webinar to learn more about mixed-signal verification and to see a practical solution created by Tanner EDA that interfaces their T-SPICE engine with Aldec Riviera-PRO simulator.  A sample Analog-to-Digital Converter design will be used to demonstrate the tools in action.

Agenda:

• Mixed-signal design flow
• SPICE-based verification advantages and disadvantages
• Digital simulation advantages and disadvantages
• Interfacing SPICE engine with digital simulator
• HiPer Simulation A/MS: the Tanner EDA mixed-signal solution

Time:11:00 AM - 12:00 PM PST