Aldec has developed a no cost Active-HDL Student Edition based on the popular Active-HDL design and simulation environment. The Student Edition is a great opportunity for students looking to use a VHDL, Verilog and SystemC simulator outside of a school lab.
Active-HDL Student Edition retains much of the same functionality, menus, and icons as the Professional or Expert Editions of this product but is limited in features and simulation capacity/performance. Aldec has created a configuration that offers a very valuable opportunity for those seeking to learn VHDL, Verilog and SystemC simulation and related logic circuit design implementation flows on their own or in addition to course instruction.
Features:
- Mixed VHDL, Verilog and SystemC Support
- Hardware Description Language Editor (HDE)
- Block Diagram Editor (BDE)
- Finite State Machine Editor (FSM)
- SystemC Interface to VHDL/Verilog models
- SystemC Transaction Wizard
- C Compilation capability
- Mathworks' Matlab™/Simulink™ Interface
- Intellectual Property (IP) Core Generator
- Export2HTML capability
- TCL/TK scripting
- Interactive VHDL and Verilog Tutorial