DO-254 document "Design Assurance Guidance for Airborne Electronic Hardware" specifies numerous requirements imposed on the process of creation airborne FPGA or ASIC designs. While there is no single tool that can guarantee compliance with DO-254, rigorously checking a set of well-selected design rules may facilitate achieving of the compliance. DO-254 VHDL and Verilog design rule plug-ins for ALINT were created based on our expertise and customer feedback in both DO-254 compliance solutions and general HDL rule checking. The DO-254 HDL Design Rules are user-configurable, well documented and easy to use.
Direct link to free 10-day evaluation copy of DO-254 HDL Design Rules plug-in to ALINT: http://www.aldec.com/Downloads/default.aspx

• Design Creation
  • Schematic / Block Diagram Editor
  • Code2Graphics
  • HDL Text Editor
  • Basic HDL Text Editor
  • State Machine Editor
  • FPGA Project Management
  • IP Core Generator
  • Testbench Generation
  • Documentation (HTML/PDF)
• Verification
  • Phase-Based Linting (PBL)
  • OVM and UVM Support
  • VHDL Simulation
  • FPGA Primitive Support
  • Verilog Simulation
  • SystemC
  • SystemVerilog
  • Assertions (PSL, SVA and OVA)
  • Verilog Simulation Optimization
  • Acceleration/Emulation
  • VHDL Simulation Optimization
  • Prototyping
  • Coverage Tools
  • Design Rule Checker
• Specialty Solutions
  • DO-254 In-Hardware Simulation
  • Code Coverage DO-254 Tool Assessment and Qualification
  • DO-254 HDL Design Rules
  • MATLAB/Simulink Co-Simulation
  • Verification IP
  • HDL Regression Manager
  • NIOS II Co-Verification
  • ARM Co-Verification
  • Actel RTAX/RTSX Prototyping
  • Actel RTSX Prototyping
  • EDIF Netlist Conversion