ALINT™, Aldec's advanced Design Rule Checking Tool helps detect a wide variety of design problems, including poor coding styles, improper clock and reset management, simulation, synthesis problems, poor testability and source code issues throughout the design flow. ALINT provides extensive checking of the quality of VHDL and Verilog® code using a set of design rules established by STARC® (The Semiconductor Technology Academic Research Center) from Japan as well as rules developed by Aldec(ALDEC, DO-254, and RMM rule plug-ins). ALINT features a unique framework that combines all necessary tools for easy set up of the design checks, linting and results analysis and debugging. Creation of custom rules is supported.

• Design Creation
  • Schematic / Block Diagram Editor
  • Code2Graphics
  • HDL Text Editor
  • Basic HDL Text Editor
  • State Machine Editor
  • FPGA Project Management
  • IP Core Generator
  • Testbench Generation
  • Documentation (HTML/PDF)
• Verification
  • Phase-Based Linting (PBL)
  • OVM and UVM Support
  • VHDL Simulation
  • FPGA Primitive Support
  • Verilog Simulation
  • SystemC
  • SystemVerilog
  • Assertions (PSL, SVA and OVA)
  • Verilog Simulation Optimization
  • Acceleration/Emulation
  • VHDL Simulation Optimization
  • Prototyping
  • Coverage Tools
  • Design Rule Checker
• Specialty Solutions
  • DO-254 In-Hardware Simulation
  • Code Coverage DO-254 Tool Assessment and Qualification
  • DO-254 HDL Design Rules
  • MATLAB/Simulink Co-Simulation
  • Verification IP
  • HDL Regression Manager
  • NIOS II Co-Verification
  • ARM Co-Verification
  • Actel RTAX/RTSX Prototyping
  • Actel RTSX Prototyping
  • EDIF Netlist Conversion