Aldec provides a hardware/software co-verification solution for verification of NIOS II-centric SoC designs. It is built around Aldec's digital logic simulators and FPGA acceleration card, connected to the Altera NIOS II IDE debugger. Aldec's patented Smart Clock technology provides engineers with an unprecedented combination of simulation speed and software/hardware debugging features with no need to modify the SoC design.

The Smart Clock solution takes care of all synchronization details and is transparent to the Avalon devices. To reduce Avalon peripherals design time, Aldec's co-verification solution allows creation of high-level C++ peripheral models using STL, Win API and other 3rd party libraries for advanced system-level co-verification. An integrated Debug Module operates as a virtual logic analyzer with 128 MB memory buffer at MHz speed.

• Design Creation
  • Schematic / Block Diagram Editor
  • Code2Graphics
  • HDL Text Editor
  • Basic HDL Text Editor
  • State Machine Editor
  • FPGA Project Management
  • IP Core Generator
  • Testbench Generation
  • Documentation (HTML/PDF)
• Verification
  • Phase-Based Linting (PBL)
  • OVM and UVM Support
  • VHDL Simulation
  • FPGA Primitive Support
  • Verilog Simulation
  • SystemC
  • SystemVerilog
  • Assertions (PSL, SVA and OVA)
  • Verilog Simulation Optimization
  • Acceleration/Emulation
  • VHDL Simulation Optimization
  • Prototyping
  • Coverage Tools
  • Design Rule Checker
• Specialty Solutions
  • DO-254 In-Hardware Simulation
  • Code Coverage DO-254 Tool Assessment and Qualification
  • DO-254 HDL Design Rules
  • MATLAB/Simulink Co-Simulation
  • Verification IP
  • HDL Regression Manager
  • NIOS II Co-Verification
  • ARM Co-Verification
  • Actel RTAX/RTSX Prototyping
  • Actel RTSX Prototyping
  • EDIF Netlist Conversion