ALDEC has developed a prototyping solution for RTAX-S/SL and RTSX-SU devices using reprogrammable flash-based ProASIC3E FPGA's (both the RTAX/RTSX and ProASIC3E device families belong to Actel). The RTAX-S/SL and RTSX-SU prototyping package includes a prototyping adaptor board that maps the footprint of the Actel ProASIC3E device to the footprint of the RTAX-S/SL and RTSX-SU device (e.g. CQ208, CQ256, CQ352, CG624). After soldering the adaptor to the PCB, the ProASC3E device can be reprogrammed through the JTAG interface connector.  
Optional RTAX/RTSX EDIF Netlist Converter software performs automatic conversion of the RTAX/RTSX EDIF netlist to ProASIC3E EDIF netlist. It replaces primitives and memories taking into the consideration differences between RTAX-S/SL and ProASIC3E architectures. This RTAX2A3P converter also performs automatic conversion of the PDC constraint files.

• Design Creation
  • Schematic / Block Diagram Editor
  • Code2Graphics
  • HDL Text Editor
  • Basic HDL Text Editor
  • State Machine Editor
  • FPGA Project Management
  • IP Core Generator
  • Testbench Generation
  • Documentation (HTML/PDF)
• Verification
  • Phase-Based Linting (PBL)
  • OVM and UVM Support
  • VHDL Simulation
  • FPGA Primitive Support
  • Verilog Simulation
  • SystemC
  • SystemVerilog
  • Assertions (PSL, SVA and OVA)
  • Verilog Simulation Optimization
  • Acceleration/Emulation
  • VHDL Simulation Optimization
  • Prototyping
  • Coverage Tools
  • Design Rule Checker
• Specialty Solutions
  • DO-254 In-Hardware Simulation
  • Code Coverage DO-254 Tool Assessment and Qualification
  • DO-254 HDL Design Rules
  • MATLAB/Simulink Co-Simulation
  • Verification IP
  • HDL Regression Manager
  • NIOS II Co-Verification
  • ARM Co-Verification
  • Actel RTAX/RTSX Prototyping
  • Actel RTSX Prototyping
  • EDIF Netlist Conversion