The State Diagram Editor is a tool designed for the graphical creation and editing of state diagrams of synchronous and asynchronous machines. Instead of writing the HDL code, you can enter the description of a logic block as a graphical state diagram. The editor will automatically generate the HDL code based on the entered graphical description. Due to the intuitive graphic form, state diagrams are easy-to-learn and far more readable than HDL code. Some features such as Multiple State Machines on a single diagram, (Full) Moore and Mealy machines Support, Hierarchical states and junctions for better legibility, Delay states for simplifying control of machine timing, Automatic HDL code generation and Automatic Testbench generation for comprehensive verification of state machine, are available in ALDEC's Active-HDL.

• Design Creation
  • Schematic / Block Diagram Editor
  • Code2Graphics
  • HDL Text Editor
  • Basic HDL Text Editor
  • State Machine Editor
  • FPGA Project Management
  • IP Core Generator
  • Testbench Generation
  • Documentation (HTML/PDF)
• Verification
  • Phase-Based Linting (PBL)
  • OVM and UVM Support
  • VHDL Simulation
  • FPGA Primitive Support
  • Verilog Simulation
  • SystemC
  • SystemVerilog
  • Assertions (PSL, SVA and OVA)
  • Verilog Simulation Optimization
  • Acceleration/Emulation
  • VHDL Simulation Optimization
  • Prototyping
  • Coverage Tools
  • Design Rule Checker
• Specialty Solutions
  • DO-254 In-Hardware Simulation
  • Code Coverage DO-254 Tool Assessment and Qualification
  • DO-254 HDL Design Rules
  • MATLAB/Simulink Co-Simulation
  • Verification IP
  • HDL Regression Manager
  • NIOS II Co-Verification
  • ARM Co-Verification
  • Actel RTAX/RTSX Prototyping
  • Actel RTSX Prototyping
  • EDIF Netlist Conversion