The In-Hardware Simulation platform combines the world class HDL Simulation tool suite (Active-HDL or Riviera-PRO) with an In-Hardware Simulation system that supports the specific target device at system speeds of up to 200 MHz. Aldec’s new approach is a superior alternative to traditional DO-254 hardware testing methods. The In-Hardware Simulation system is based on Aldec’s Hardware Emulation System (HES) patented technology (U.S. Patent 5,479,355) and consists of the following three elements:
 

1. PCI Main Board

The PCI main board controls communication between the HDL simulator and the custom daughter board containing the target devices. The main board connects to the PC/workstation through the PCI/PCIe port. The board has its own FPGA device with the control and glue logic to handle the communication between the daughter board and the simulator. The board is preconfigured to meet the customer’s design requirements and does not contain any customer-specific devices.

2. Daughter Board

The daughter board is the hardware board with the customer specific target device (FPGA, PLD, or ASIC) which is identical to the device used in the final product. The daughter board is connected to the main board through the daughter board connector pins.

3. Compliance Verification Tool (CVT) software package

The CVT software package provides the hardware board drivers for the interface from the HDL simulator to the PCI main board. It also contains hardware configuration files, diagnostic utilities, and an application to simplify and automate the system setup for first-time use.
To begin In-Hardware testing, the designer will need to create the test vectors and generate the target FPGA or PLD bit-file. Aldec provides a plug-in to your simulator that automatically dumps test vectors from the testbench during HDL simulation. The device bit-file will be created by the P&R tool, and using the vendor-supplied programming cable, the bit-file will be downloaded to the target device on the daughter board. After this setup, In-Hardware testing can begin. The CVT software writes the input vectors to FIFO IN on the PCI Main Board, as shown in Figure 3. The CVT initiates the testing and transfers the input vectors to the target device on the daughter board. The target device generates the output vectors which are then stored in FIFO OUT on the PCI Main Board. The CVT software retrieves the output vectors and converts them to the waveform format for viewing and comparison to the waveform outputs from HDL simulation. The design functionality is considered proven if the output waveforms of In-Hardware testing match the waveforms generated during functional simulation.

• Design Creation
  • Schematic / Block Diagram Editor
  • Code2Graphics
  • HDL Text Editor
  • Basic HDL Text Editor
  • State Machine Editor
  • FPGA Project Management
  • IP Core Generator
  • Testbench Generation
  • Documentation (HTML/PDF)
• Verification
  • Phase-Based Linting (PBL)
  • OVM and UVM Support
  • VHDL Simulation
  • FPGA Primitive Support
  • Verilog Simulation
  • SystemC
  • SystemVerilog
  • Assertions (PSL, SVA and OVA)
  • Verilog Simulation Optimization
  • Acceleration/Emulation
  • VHDL Simulation Optimization
  • Prototyping
  • Coverage Tools
  • Design Rule Checker
• Specialty Solutions
  • DO-254 In-Hardware Simulation
  • Code Coverage DO-254 Tool Assessment and Qualification
  • DO-254 HDL Design Rules
  • MATLAB/Simulink Co-Simulation
  • Verification IP
  • HDL Regression Manager
  • NIOS II Co-Verification
  • ARM Co-Verification
  • Actel RTAX/RTSX Prototyping
  • Actel RTSX Prototyping
  • EDIF Netlist Conversion