Programmable logic devices are continuing to be key components of high performance digital signal processing (DSP) systems. Aldec's separate co-simulation interfaces with both Matlab and Simulink integrates MathWorks’ intuitive language and technical computing environment with Aldec's HDL-based simulation environments for FPGA and ASIC designs. Interface with Simulink allows bidirectional co-simulation of functional blocks from Simulinks library of components with VHDL or Verilog blocks simulated by Active-HDL or Riviera-PRO. Interface with Matlab (Simulink installation not required) allows execution of MATLAB commands, call M-Function, or transfer data to or from the MATLAB workspace from within an HDL code source. Communication with MATLAB is accomplished with a dedicated set of subprograms prepared for both Verilog and VHDL. At any level of a designs hierarchy, one can pass commands to MATLAB (e.g. pass an expression to solve or call M-function), transfer HDL variables to MATLAB workspace, perform necessary operations, and transfer the results back to Aldes's HDL simulator.

• Design Creation
  • Schematic / Block Diagram Editor
  • Code2Graphics
  • HDL Text Editor
  • Basic HDL Text Editor
  • State Machine Editor
  • FPGA Project Management
  • IP Core Generator
  • Testbench Generation
  • Documentation (HTML/PDF)
• Verification
  • Phase-Based Linting (PBL)
  • OVM and UVM Support
  • VHDL Simulation
  • FPGA Primitive Support
  • Verilog Simulation
  • SystemC
  • SystemVerilog
  • Assertions (PSL, SVA and OVA)
  • Verilog Simulation Optimization
  • Acceleration/Emulation
  • VHDL Simulation Optimization
  • Prototyping
  • Coverage Tools
  • Design Rule Checker
• Specialty Solutions
  • DO-254 In-Hardware Simulation
  • Code Coverage DO-254 Tool Assessment and Qualification
  • DO-254 HDL Design Rules
  • MATLAB/Simulink Co-Simulation
  • Verification IP
  • HDL Regression Manager
  • NIOS II Co-Verification
  • ARM Co-Verification
  • Actel RTAX/RTSX Prototyping
  • Actel RTSX Prototyping
  • EDIF Netlist Conversion