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Design Creation
Schematic / Block Diagram Editor
Code2Graphics
HDL Text Editor
Basic HDL Text Editor
State Machine Editor
FPGA Project Management
IP Core Generator
Testbench Generation
Documentation (HTML/PDF)
Verification
Phase-Based Linting (PBL)
OVM and UVM Support
VHDL Simulation
FPGA Primitive Support
Verilog Simulation
SystemC
SystemVerilog
Assertions (PSL, SVA and OVA)
Verilog Simulation Optimization
Acceleration/Emulation
VHDL Simulation Optimization
Prototyping
Coverage Tools
Design Rule Checker
Specialty Solutions
DO-254 In-Hardware Simulation
Code Coverage DO-254 Tool Assessment and Qualification
DO-254 HDL Design Rules
MATLAB/Simulink Co-Simulation
Verification IP
HDL Regression Manager
NIOS II Co-Verification
ARM Co-Verification
Actel RTAX/RTSX Prototyping
Actel RTSX Prototyping
EDIF Netlist Conversion
Related Products
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