All ALDEC simulators provide full support of the IEEE 1364-2005 Verilog Standard.  To enable simulation of a large variety of designs, both legacy and new, our simulators can be set to work in Verilog ’95, 2001 and 2005 modes. The Verilog PLI (Programming Language Interface) and VPI (Verilog Procedural Interface) are supported as described in the IEEE 1364 Standard, allowing a mechanism to access and modify data in a simulated Verilog model. For greater convenience, ALDEC simulators are equipped with options that allow optimization of simulations for maximal speed or extensive debugging while strictly adhering to IEEE Standards.

• Design Creation
  • Schematic / Block Diagram Editor
  • Code2Graphics
  • HDL Text Editor
  • Basic HDL Text Editor
  • State Machine Editor
  • FPGA Project Management
  • IP Core Generator
  • Testbench Generation
  • Documentation (HTML/PDF)
• Verification
  • Phase-Based Linting (PBL)
  • OVM and UVM Support
  • VHDL Simulation
  • FPGA Primitive Support
  • Verilog Simulation
  • SystemC
  • SystemVerilog
  • Assertions (PSL, SVA and OVA)
  • Verilog Simulation Optimization
  • Acceleration/Emulation
  • VHDL Simulation Optimization
  • Prototyping
  • Coverage Tools
  • Design Rule Checker
• Specialty Solutions
  • DO-254 In-Hardware Simulation
  • Code Coverage DO-254 Tool Assessment and Qualification
  • DO-254 HDL Design Rules
  • MATLAB/Simulink Co-Simulation
  • Verification IP
  • HDL Regression Manager
  • NIOS II Co-Verification
  • ARM Co-Verification
  • Actel RTAX/RTSX Prototyping
  • Actel RTSX Prototyping
  • EDIF Netlist Conversion