The verification process is becoming more and more difficult with the increasing size and complexity of design under tight schedule. To help designers overcome this challenge, ALDEC, provides tools that automate testbench creation as well as support for testbenches that generate randomized, constrained stimulus. Our tools facilitate simple to-use, point-and-click tools as well as advanced C-based methodologies to generate testbenches.

Generating testbenches from waveform files will allow designers to translate a waveform file into a testbench which is editable for reuse. Automatic generation of testbenches for state machines allows you to create a testbench that fully tests the state machine. The SystemC Verification Library (SCV) delivered with ALDEC tools allows creating constrained and randomized stimulus. SCV combined with the transactor methodology offers the designer a powerful tool to create advanced testbench that automatically generated stimulus as well.

• Design Creation
  • Schematic / Block Diagram Editor
  • Code2Graphics
  • HDL Text Editor
  • Basic HDL Text Editor
  • State Machine Editor
  • FPGA Project Management
  • IP Core Generator
  • Testbench Generation
  • Documentation (HTML/PDF)
• Verification
  • Phase-Based Linting (PBL)
  • OVM and UVM Support
  • VHDL Simulation
  • FPGA Primitive Support
  • Verilog Simulation
  • SystemC
  • SystemVerilog
  • Assertions (PSL, SVA and OVA)
  • Verilog Simulation Optimization
  • Acceleration/Emulation
  • VHDL Simulation Optimization
  • Prototyping
  • Coverage Tools
  • Design Rule Checker
• Specialty Solutions
  • DO-254 In-Hardware Simulation
  • Code Coverage DO-254 Tool Assessment and Qualification
  • DO-254 HDL Design Rules
  • MATLAB/Simulink Co-Simulation
  • Verification IP
  • HDL Regression Manager
  • NIOS II Co-Verification
  • ARM Co-Verification
  • Actel RTAX/RTSX Prototyping
  • Actel RTSX Prototyping
  • EDIF Netlist Conversion