Press Release	Aldec supports OVM and UVM in Riviera-PRO		View
Presentation	Building a SystemVerilog Testbench		View
Presentation	OVM/UVM for FPGAs: The End of Burn and Churn		View
How-To Guide	Getting Started with OVM/UVM using Riviera-PRO		View
Product	Riviera-PRO Download		Download

Open Verification Methodology (OVM) is the library of procedures for stimulus generation, data collection and control of verification. Available in SystemVerilog and SystemC, OVM allows easy creation of directed or random test utilizing transaction-level communication and Functional Coverage.

Universal Verification Methodology (UVM) is the latest project reconciling OVM with the competing VMM methodology. It promises to improve testbench reuse, make verification code more portable and create new market for universal, high-quality Verification IP (Intellectual Property).

• Design Creation
  • Schematic / Block Diagram Editor
  • Code2Graphics
  • HDL Text Editor
  • Basic HDL Text Editor
  • State Machine Editor
  • FPGA Project Management
  • IP Core Generator
  • Testbench Generation
  • Documentation (HTML/PDF)
• Verification
  • Phase-Based Linting (PBL)
  • OVM and UVM Support
  • VHDL Simulation
  • FPGA Primitive Support
  • Verilog Simulation
  • SystemC
  • SystemVerilog
  • Assertions (PSL, SVA and OVA)
  • Verilog Simulation Optimization
  • Acceleration/Emulation
  • VHDL Simulation Optimization
  • Prototyping
  • Coverage Tools
  • Design Rule Checker
• Specialty Solutions
  • DO-254 In-Hardware Simulation
  • Code Coverage DO-254 Tool Assessment and Qualification
  • DO-254 HDL Design Rules
  • MATLAB/Simulink Co-Simulation
  • Verification IP
  • HDL Regression Manager
  • NIOS II Co-Verification
  • ARM Co-Verification
  • Actel RTAX/RTSX Prototyping
  • Actel RTSX Prototyping
  • EDIF Netlist Conversion