IP Core Generator tools built-into ALDEC products come with a rich set of parameterized modules. They are ready-to-use in any VHDL or Verilog based system. Each generated module is IC vendor independent and can be adjusted to the user's requirements. All modules can be synthesized in any commercial synthesis tool with very good results of speed and area. They also can be used in any CPLD or FPGA technologies. Salient features of Aldec's IP Core Generator are Simple, intuitive user interface (Select a module, set parameters, generate VHDL or Verilog code, and save it to the file) Simple VHDL and Verilog style coding that is compliant to IEEE Standards. Generated VHDL and Verilog code is optimized for a number of vendors and can be synthesized in any of the popular synthesis tools.

• Design Creation
  • Schematic / Block Diagram Editor
  • Code2Graphics
  • HDL Text Editor
  • Basic HDL Text Editor
  • State Machine Editor
  • FPGA Project Management
  • IP Core Generator
  • Testbench Generation
  • Documentation (HTML/PDF)
• Verification
  • Phase-Based Linting (PBL)
  • OVM and UVM Support
  • VHDL Simulation
  • FPGA Primitive Support
  • Verilog Simulation
  • SystemC
  • SystemVerilog
  • Assertions (PSL, SVA and OVA)
  • Verilog Simulation Optimization
  • Acceleration/Emulation
  • VHDL Simulation Optimization
  • Prototyping
  • Coverage Tools
  • Design Rule Checker
• Specialty Solutions
  • DO-254 In-Hardware Simulation
  • Code Coverage DO-254 Tool Assessment and Qualification
  • DO-254 HDL Design Rules
  • MATLAB/Simulink Co-Simulation
  • Verification IP
  • HDL Regression Manager
  • NIOS II Co-Verification
  • ARM Co-Verification
  • Actel RTAX/RTSX Prototyping
  • Actel RTSX Prototyping
  • EDIF Netlist Conversion