Even the most experienced designers and verification engineers can make mistakes, especially those yielding false positive results during simulation. ALDEC Simulators support advanced Coverage Tools that help engineers to avoid those costly mistakes. Coverage tools analyze execution of the source code (Code Coverage, including line, statement, branch, expression and condition coverage) and behavior of the objects described in the code (Assertion Coverage and Toggle Coverage). Line and statement coverage allow quick identification of dead design code (or inefficiently written testbench). Branch coverage informs about untested branches of ‘if’ and ‘case’ statements, which suggest improvements to the verification algorithm. Expression and Condition coverage help to discover coding errors and indicate less-than-perfect testbenches. Assertions Coverage improves visibility of assert and cover statements by providing statistics of their successful, attempted and failed evaluations. Toggle Coverage shows how frequently selected signals in the design hierarchy change their value, providing quick indication of verification success or failure.

Coverage data can be saved to an ACDB (Aldec Coverage DataBase) file which is unified storage format for coverage data of different types.

Dedicated Code and Toggle Coverage Viewers are available for efficient coverage data analysis.

• Design Creation
  • Schematic / Block Diagram Editor
  • Code2Graphics
  • HDL Text Editor
  • Basic HDL Text Editor
  • State Machine Editor
  • FPGA Project Management
  • IP Core Generator
  • Testbench Generation
  • Documentation (HTML/PDF)
• Verification
  • Phase-Based Linting (PBL)
  • OVM and UVM Support
  • VHDL Simulation
  • FPGA Primitive Support
  • Verilog Simulation
  • SystemC
  • SystemVerilog
  • Assertions (PSL, SVA and OVA)
  • Verilog Simulation Optimization
  • Acceleration/Emulation
  • VHDL Simulation Optimization
  • Prototyping
  • Coverage Tools
  • Design Rule Checker
• Specialty Solutions
  • DO-254 In-Hardware Simulation
  • Code Coverage DO-254 Tool Assessment and Qualification
  • DO-254 HDL Design Rules
  • MATLAB/Simulink Co-Simulation
  • Verification IP
  • HDL Regression Manager
  • NIOS II Co-Verification
  • ARM Co-Verification
  • Actel RTAX/RTSX Prototyping
  • Actel RTSX Prototyping
  • EDIF Netlist Conversion