The HDL Editor is a text editor designed for editing C/C++ or HDL source code. It is tightly integrated with the compiler and simulator to enable debugging capabilities. To facilitate work with source code, the editor features: Keyword coloring for VHDL, Verilog and C++/Handel-C/SystemC source code, Automated completion of keywords, Context-sensitive help (F1) on VHDL and Verilog, reserved keywords, Navigation with bookmarks, Uppercase/Lowercase editing, Column Selection, Automatic division of source code into groups according to the VHDL and Verilog syntax, recording and playing actions and is tightly integrated with the waveform viewer and debugging tools. Signals can also be added to the waveform and dataflow window directly from the HDL editor.

• Design Creation
  • Schematic / Block Diagram Editor
  • Code2Graphics
  • HDL Text Editor
  • Basic HDL Text Editor
  • State Machine Editor
  • FPGA Project Management
  • IP Core Generator
  • Testbench Generation
  • Documentation (HTML/PDF)
• Verification
  • Phase-Based Linting (PBL)
  • OVM and UVM Support
  • VHDL Simulation
  • FPGA Primitive Support
  • Verilog Simulation
  • SystemC
  • SystemVerilog
  • Assertions (PSL, SVA and OVA)
  • Verilog Simulation Optimization
  • Acceleration/Emulation
  • VHDL Simulation Optimization
  • Prototyping
  • Coverage Tools
  • Design Rule Checker
• Specialty Solutions
  • DO-254 In-Hardware Simulation
  • Code Coverage DO-254 Tool Assessment and Qualification
  • DO-254 HDL Design Rules
  • MATLAB/Simulink Co-Simulation
  • Verification IP
  • HDL Regression Manager
  • NIOS II Co-Verification
  • ARM Co-Verification
  • Actel RTAX/RTSX Prototyping
  • Actel RTSX Prototyping
  • EDIF Netlist Conversion