The sheer size of designs, number of tools used and the number of people involved makes FPGA Project management a challenge. With ALDEC tools this challenge is easily overcome. ALDEC tools organize project files into logical sets, create design hierarchy,  merge source files into a single file, remembers the compilation order, manage multiple design libraries, manage all information related to a design or multiple designs contained within a workspace. It facilitates configuration of compilation and simulation processes, while handling and organizing source and log files that are created throughout consecutive design phases. To enable efficient teamwork and ensure proper control of changes introduced by the design group members, archiving utilities and an interface to source revision control systems have been incorporated into the ALDEC tools.

• Design Creation
  • Schematic / Block Diagram Editor
  • Code2Graphics
  • HDL Text Editor
  • Basic HDL Text Editor
  • State Machine Editor
  • FPGA Project Management
  • IP Core Generator
  • Testbench Generation
  • Documentation (HTML/PDF)
• Verification
  • Phase-Based Linting (PBL)
  • OVM and UVM Support
  • VHDL Simulation
  • FPGA Primitive Support
  • Verilog Simulation
  • SystemC
  • SystemVerilog
  • Assertions (PSL, SVA and OVA)
  • Verilog Simulation Optimization
  • Acceleration/Emulation
  • VHDL Simulation Optimization
  • Prototyping
  • Coverage Tools
  • Design Rule Checker
• Specialty Solutions
  • DO-254 In-Hardware Simulation
  • Code Coverage DO-254 Tool Assessment and Qualification
  • DO-254 HDL Design Rules
  • MATLAB/Simulink Co-Simulation
  • Verification IP
  • HDL Regression Manager
  • NIOS II Co-Verification
  • ARM Co-Verification
  • Actel RTAX/RTSX Prototyping
  • Actel RTSX Prototyping
  • EDIF Netlist Conversion